FPGA power reduction using configurable dual-Vdd. - Fei Li 003; Yan Lin 001; Lei He 001 (DAC, 2004)

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. - Fei Li 003; Yan Lin 001; Lei He 001; Jason Cong (FPGA, 2004)

Vdd programmability to reduce FPGA interconnect power. - Fei Li 003; Yan Lin 001; Lei He 001 (ICCAD, 2004)

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. - Yan Lin 001; Fei Li 003; Lei He 001 (ASP-DAC, 2005)

Device and architecture co-optimization for FPGA power reduction. - Lerong Cheng; Phoebe Wong; Fei Li 003; Yan Lin 001; Lei He 001 (DAC, 2005)

Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. - Yan Lin 001; Lei He 001 (DAC, 2005)

Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. - Yan Lin 001; Fei Li 003; Lei He 001 (FPGA, 2005)

FPGA device and architecture evaluation considering process variations. - Ho-Yan Wong; Lerong Cheng; Yan Lin 001; Lei He 001 (ICCAD, 2005)

Circuits and architectures for field programmable gate array with configurable supply voltage. - Yan Lin 001; Fei Li 003; Lei He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. - Yu Hu 002; Yan Lin 001; Lei He 001; Tim Tuan (DAC, 2006)

Placement and Timing for FPGAs Considering Variations. - Mike Hutton; Yan Lin 001; Lei He 001 (FPL, 2006)

An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. - Yan Lin 001; Yu Hu 002; Lei He 001; Vijay Raghunat (ISLPED, 2006)

Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. - Yan Lin 001; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. - Yan Lin 001; Lei He 001 (DATE, 2007)

Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. - Yan Lin 001; Lei He 001 (FPGA, 2007)

Device and architecture concurrent optimization for FPGA transient soft error rate. - Yan Lin 001; Lei He 001 (ICCAD, 2007)

Statistical placement for FPGAs considering. - Yan Lin 001; Mike Hutton; Lei He 001 (IET Comput. Digit. Tech., 2007)

Device and Architecture Cooptimization for FPGA Power Reduction. - Lerong Cheng; Fei Li 003; Yan Lin 001; Phoebe Wong; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Field Programmability of Supply Voltages for FPGA Power Reduction. - Fei Li 003; Yan Lin 001; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. - Lerong Cheng; Yan Lin 001; Lei He 001 (FPGA, 2008)

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. - Yu Hu 002; Yan Lin 001; Lei He 001; Tim Tuan (ACM Trans. Design Autom. Electr. Syst., 2008)

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. - Yan Lin 001; Lei He 001; Mike Hutton (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Statistical Timing and Power Optimization of Architecture and Device for FPGAs. - Lerong Cheng; Wenyao Xu; Fang Gong; Yan Lin 001; Ho-Yan Wong; Lei He 001 (ACM Trans. Reconfigurable Technol. Syst., 2012)