A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS. - Peifang Wu; Yan Liu 088; Xi Feng; Hao Xu 005; Na Yan 004 (ASICON, 2023)

INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications. - Haoyuan Gao; Hao Xu 005; Xinyi Lin; Yan Liu 088; Zhidong Tang; Xufeng Kou; Xingyu Zhang; Tetsuya Iizuka; Na Yan 004 (ICTA, 2023)

An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS. - Yizhuo Wang; Hao Xu 005; Guoyu Li; Shuai Liu; Yan Liu 088; Rui Yin; Hui Pan; Na Yan 004 (CICC, 2024)

A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques. - Yan Liu 088; Haoyuan Gao; Hao Xu 005; Ping Lu 002; Na Yan 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving -269.9-dB FoMJitter-N-Area. - Haoyuan Gao; Yan Liu 088; Peifang Wu; Jiao Liu; Yiyun Mao; Xinyi Lin; Rui Yin; Ping Lu 002; Long Kong; Na Yan 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)