A scalable and fault-tolerant routing algorithm for NoCs. - Zewen Shi; Kaidi You; Yan Ying; Bei Huang; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2010)

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue. - Yan Ying; Dan Bao; Zhiyi Yu; Xiaoyang Zeng; Yun Chen 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications. - Dan Bao; Chuan Wu; Yan Ying; Yun Chen 001; Xiaoyang Zeng (ASP-DAC, 2011)

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. - Yan Ying; Kaidi You; Liyang Zhou; Heng Quan; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. - Zhiyi Yu; Kaidi You; Ruijin Xiao; Heng Quan; Peng Ou; Yan Ying; Haofan Yang 001; Ming-e Jing; Xiaoyang Zeng (ISSCC, 2012)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)