A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. - Tsung-Yi Tsai; Yan-You Chou; Chua-Chin Wang (ICICDT, 2016)

2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; Yan-You Chou; Tzung-Je Lee (Circuits Syst. Signal Process., 2021)