PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. - Qize Yang; Taiquan Wei; Sihan Guan; Chengran Li; Haoran Shang; Jinyi Deng; Huizheng Wang; Chao Li 009; Lei Wang; Yan Zhang 163; Shouyi Yin; Yang Hu 001 (ISCA, 2025)