Flexible Core Reallocation for Virtex II Structures. - Yana Esteves Krasteva; Ana B. Jimeno; Eduardo de la Torre; Teresa Riesgo (ERSA, 2005)

Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. - Yana Esteves Krasteva; Ana B. Jimeno; Eduardo de la Torre; Teresa Riesgo (IEEE International Workshop on Rapid System Prototyping, 2005)

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo; Didier Joly (FPL, 2006)

Partial Reconfiguration for Core Reallocation and Flexible Communications. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2006)

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ISCAS, 2007)

A Fast Emulation-Based NoC Prototyping Framework. - Yana Esteves Krasteva; Francisco Criado; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2008)

Generic Systolic Array for Run-Time Scalable Cores. - Andrés Otero; Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (ARC, 2010)

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. - Andrés Otero; Eduardo de la Torre; Teresa Riesgo; Yana Esteves Krasteva (FPL, 2010)

Reconfigurable Networks on Chip: DRNoC architecture. - Yana Esteves Krasteva; Eduardo de la Torre; Teresa Riesgo (J. Syst. Archit., 2010)