Automatic selection of application-specific instruction-set extensions. - Carlo Galuzzi; Elena Moscu Panainte; Yana Yankova; Koen Bertels; Stamatis Vassiliadis (CODES+ISSS, 2006)

HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. - Koen Bertels; Georgi Kuzmanov; Elena Moscu Panainte; Georgi Gaydadjiev; Yana Yankova; Vlad Mihai Sima; Kamana Sigdel; Roel Meeuws; Stamatis Vassiliadis (FPL, 2007)

A Quantitative Prediction Model for Hardware/Software Partitioning. - Roel Meeuws; Yana Yankova; Koen Bertels; Georgi Gaydadjiev; Stamatis Vassiliadis (FPL, 2007)

DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. - Yana Yankova; Koen Bertels; Georgi Kuzmanov; Georgi Gaydadjiev; Yi Lu 004; Stamatis Vassiliadis (FPL, 2007)

Automated HDL Generation: Comparative Evaluation. - Yana Yankova; Koen Bertels; Stamatis Vassiliadis; Roel Meeuws; Arcilio Virginia (ISCAS, 2007)

High level quantitative interconnect estimation for Early Design Space Exploration. - Roel Meeuws; Kamana Sigdel; Yana Yankova; Koen Bertels (FPT, 2008)

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. - Koen Bertels; Vlad Mihai Sima; Yana Yankova; Georgi Kuzmanov; Wayne Luk; José Gabriel F. Coutinho; Fabrizio Ferrandi; Christian Pilato; Marco Lattuada 001; Donatella Sciuto; Andrea Michelotti (IEEE Micro, 2010)

DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler. - Razvan Nane; Vlad Mihai Sima; Bryan Olivier; Roel Meeuws; Yana Yankova; Koen Bertels (FPL, 2012)