Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors. - Yanan Sun 003; Volkan Kursun (ISCAS, 2011)

Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs. - Yanan Sun 003; Volkan Kursun (VLSI-SoC, 2011)

NP dynamic CMOS resurrection with carbon nanotube field effect transistors. - Yanan Sun 003; Volkan Kursun (ISOCC, 2012)

Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors. - Yanan Sun 003; Volkan Kursun (ISCAS, 2013)

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. - Yanan Sun 003; Hailong Jiao; Volkan Kursun (ICM, 2014)

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits. - Yanan Sun 003; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed. - Yanan Sun 003; Volkan Kursun (ISCAS, 2015)

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors. - Yanan Sun 003; Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. - Naifeng Jing; Taozhong Li; Zhongyuan Zhao 004; Wei Jin 004; Yanan Sun 003; Weifeng He; Zhigang Mao (FPT, 2016)

Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme. - Ling Chen; Yanan Sun 003; Weifeng He (ASICON, 2017)

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ASICON, 2017)

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. - Wei Jin 004; Weifeng He; Jianfei Jiang 001; Haichao Huang; Xuejun Zhao; Yanan Sun 003; Xin Chen; Naifeng Jing (Integr., 2017)

Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. - Yanan Sun 003; Weifeng He; Zhigang Mao; Volkan Kursun (Microelectron. J., 2017)

Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array. - Pengfei Ji; Jing Gao; Wenyi Xu; Yanan Sun 003; Weifeng He; Hui Wu (ISCAS, 2018)

Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit. - Chen Wang 072; Yanan Sun 003; Shiyan Hu 001; Li Jiang 002; Weikang Qian (ACM Trans. Design Autom. Electr. Syst., 2018)

Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. - Jiachen Jiang; Yanan Sun 003; Weifeng He; Zhigang Mao; Volkan Kursun (ASICON, 2019)

Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ICEIC, 2019)

A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. - Yongjie Lu; Yanan Sun 003; Weifeng He; Zhigang Mao (NANOARCH, 2019)

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. - Yanan Sun 003; Jiawei Gu; Weifeng He; Qin Wang 009; Naifeng Jing; Zhigang Mao; Weikang Qian; Li Jiang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing. - Chang Ma; Yanan Sun 003; Weikang Qian; Ziqi Meng; Rui Yang; Li Jiang 002 (DATE, 2020)

ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory. - Zhuoran Song; Yilong Zhao; Yanan Sun 003; Xiaoyao Liang; Li Jiang 002 (ACM Great Lakes Symposium on VLSI, 2020)

25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Bingxi Pei; Zhigang Mao; Mingoo Seok (ISSCC, 2020)

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Zhigang Mao; Mingoo Seok (DAC, 2021)

Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation. - Ziqi Meng; Weikang Qian; Yilong Zhao; Yanan Sun 003; Rui Yang; Li Jiang 002 (DATE, 2021)

An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. - Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (ICCAD, 2021)

A Ternary Memristive Logic-in-Memory Design for Fast Data Scan. - Tianhong Shen; Yanan Sun 003; Weifeng He; Zhi Li 058; Weiyi Liu; Zhezhi He; Li Jiang 002 (ICTA, 2021)

Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap? - Runsheng Wang; Zuodong Zhang; Yawen Zhang; Yixuan Hu; Yanan Sun 003; Weikang Qian; Ru Huang 001 (IRPS, 2021)

Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process. - Jieyu Li; Zihan Lian; Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (ISCAS, 2021)

Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. - Weiyi Liu; Yanan Sun 003; Weifeng He; Qin Wang 009 (ISCAS, 2021)

An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. - Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (ISCAS, 2021)

An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM. - Hao Zhang 151; Jieyu Li; Weifeng He; Yanan Sun 003; Mingoo Seok (ISCAS, 2021)

MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Bingxi Pei; Pavan Kumar Chundi; Zhigang Mao; Mingoo Seok (IEEE J. Solid State Circuits, 2021)

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing. - Yanan Sun 003; Chang Ma; Zhi Li 058; Yilong Zhao; Jiachen Jiang; Weikang Qian; Rui Yang; Zhezhi He; Li Jiang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator. - Zhuoran Song; Yanan Sun 003; Lerong Chen; Tianjian Li; Naifeng Jing; Xiaoyao Liang; Li Jiang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Write or not: programming scheme optimization for RRAM-based neuromorphic computing. - Ziqi Meng; Yanan Sun 003; Weikang Qian (DAC, 2022)

CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. - Liukai Xu; Songyuan Liu; Zhi Li 058; Dengfeng Wang; Yiming Chen; Yanan Sun 003; Xueqing Li 002; Weifeng He; Shi Xu (DAC, 2022)

All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations. - Dengfeng Wanq; Zhi Li 058; Chengjun Chang; Weifeng He; Yanan Sun 003 (ICTA, 2022)

An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy. - Jianfeng Wang; Nuo Xiu; Juejian Wu; Yiming Chen; Yanan Sun 003; Huazhong Yang; Vijaykrishnan Narayanan; Sumitha George; Xueqing Li 002 (ISCAS, 2022)

MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. - Shuai Yuan 016; Yanan Sun 003; Weifeng He; Qianrong Gu; Shi Xu; Zhigang Mao; Shikui Tu (IEEE Trans. Geosci. Remote. Sens., 2022)

DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network. - Dengwei Zhao; Shuai Yuan 016; Yanan Sun 003; Shikui Tu; Lei Xu 001 (DATE, 2023)

TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. - Dengfeng Wang; Liukai Xu; Songyuan Liu; Zhi Li 058; Yiming Chen; Weifeng He; Xueqing Li 002; Yanan Sun 003 (ICCAD, 2023)

High Energy-Efficient Approximate In-SRAM Computing with Bit-Wise Compressor Configuration and Data-Aware Weight Remapping Method for Neural Network Acceleration. - Shunqin Cai; Liukai Xu; Dengfeng Wang; Zhi Li 058; Liang Chang; Yanan Sun 003 (ICTA, 2023)

CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration. - Yanan Sun 003; Dengfeng Wang; Liukai Xu; Yiming Chen; Zhi Li 058; Songyuan Liu; Weifeng He; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead. - Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. - Yanan Sun 003; Zhi Li 058; Weiyi Liu; Weifeng He; Qin Wang 009; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. - Yuxuan Qin; Chuxiong Lin; Weifeng He; Yanan Sun 003; Zhigang Mao; Mingoo Seok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration. - Liukai Xu; Shuai Yuan 016; Dengfeng Wang; Yiming Chen; Xueqing Li 002; Yanan Sun 003 (DAC, 2024)

An Energy-Efficient Logarithmic-Posit-Based In-SRAM Computing for Neural Network Acceleration. - Chengjun Chang; Liukai Xu; Dengfeng Wang; Yanan Sun 003 (ICTA, 2024)

A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Lin Shao; Bo Zhang 105; Jun Yang 006; Mingoo Seok (IEEE J. Solid State Circuits, 2024)

VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations. - Chen Nie; Chenyu Tang; Jie Lin 004; Huan Hu; Chenyang Lv; Ting Cao; Weifeng Zhang 003; Li Jiang 002; Xiaoyao Liang; Weikang Qian; Yanan Sun 003; Zhezhi He (IEEE Trans. Computers, 2024)

Robust Monolithic 3D Carbon-Based Computing-in-SRAM With Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density. - Dengfeng Wang; Weifeng He; Qin Wang 009; Hailong Jiao; Yanan Sun 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

HyCTor: A Hybrid CNN-Transformer Network Accelerator With Flexible Weight/Output Stationary Dataflow and Multicore Extension. - Shuai Yuan 016; Weifeng He; Zhenhua Zhu; Fangxin Liu; Zhuoran Song; Guohao Dai; Guanghui He; Yanan Sun 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator. - Zhican Wang; Hongxiang Fan; Haroon Waris; Gang Wang; Zhenyu Li; Jianfei Jiang 001; Yanan Sun 003; Guanghui He (CoRR, 2025)