Single-Loop Delta-Sigma ADC Using Noise-Coupled VCO Quantizer. - Mahmoud Sadollahi; Lukang Shi; Yanchao Wang 001; Gabor C. Temes (MWSCAS, 2018)

A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC. - Lukang Shi; Yi Zhang 023; Yanchao Wang 001; Manjunath Kareppagoudr; Mahmoud Sadollahi; Gabor C. Temes (MWSCAS, 2018)

Robust Continuous-Time MASH Delta Sigma Modulator. - Yanchao Wang 001; Lukang Shi; Tao He 001; Yi Zhang 023; Chia-Hung Chen; Gabor C. Temes (MWSCAS, 2018)

Passive slew rate enhancement technique for Switched-Capacitor Circuits. - Manjunath Kareppagoudr; Emanuel Caceres; Yu-Wen Kuo; Jyotindra R. Shakya; Yanchao Wang 001; Gabor C. Temes (MWSCAS, 2019)

Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial. - Pedram Payandehnia; Tao He 001; Yanchao Wang 001; Gabor C. Temes (CICC, 2020)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)