An Enhanced Time-Reversal Imaging Algorithm-Driven Sparse Linear Array for Progressive and Quantitative Monitoring of Cracks. - Qiang Wang 014; Yanfeng Xu; Zhongqing Su; Maosen Cao; Dong Yue 001 (IEEE Trans. Instrum. Meas., 2019)

An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping. - Yewei Zhang; Kejie Huang; Rui Xiao; Bo Wang 020; Yanfeng Xu; Jicong Fan 002; Haibin Shen (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights. - Rui Xiao; Yewei Zhang; Bo Wang 020; Yanfeng Xu; Jicong Fan 002; Haibin Shen; Kejie Huang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration. - Yonggen Li; Xin Li; Haibin Shen; Jicong Fan 002; Yanfeng Xu; Kejie Huang (ACM Trans. Reconfigurable Technol. Syst., 2024)