Mixed-level modeling for network on chip infrastructure in SoC design. - Yang Hu 001; Shouyi Yin; Leibo Liu; Shaojun Wei (APCCAS, 2010)

Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC. - Shouyi Yin; Yang Hu 001; Zhen Zhang; Leibo Liu; Shaojun Wei (IEICE Trans. Electron., 2012)

Enabling datacenter servers to scale out economically and sustainably. - Chao Li 009; Yang Hu 001; Ruijin Zhou; Ming Liu 006; Longjun Liu; Jingling Yuan; Tao Li 006 (MICRO, 2013)

Leveraging distributed UPS energy for managing solar energy powered data centers. - Longjun Liu; Hongbin Sun 001; Yang Hu 001; Jingmin Xin; Nanning Zheng 001; Tao Li 006 (IGCC, 2014)

Towards Automated Provisioning and Emergency Handling in Renewable Energy Powered Datacenters. - Chao Li 009; Rui Wang 014; Yang Hu 001; Ruijin Zhou; Ming Liu 006; Longjun Liu; Jingling Yuan; Tao Li 006; Depei Qian (J. Comput. Sci. Technol., 2014)

BAAT: Towards Dynamically Managing Battery Aging in Green Datacenters. - Longjun Liu; Chao Li 009; Hongbin Sun 001; Yang Hu 001; Juncheng Gu; Tao Li 006 (DSN, 2015)

Towards sustainable in-situ server systems in the big data era. - Chao Li 009; Yang Hu 001; Longjun Liu; Juncheng Gu; Mingcong Song; Xiaoyao Liang; Jingling Yuan; Tao Li 006 (ISCA, 2015)

HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy. - Longjun Liu; Chao Li 009; Hongbin Sun 001; Yang Hu 001; Juncheng Gu; Tao Li 006; Jingmin Xin; Nanning Zheng 001 (ISCA, 2015)

Leveraging Heterogeneous Power for Improving Datacenter Efficiency and Resiliency. - Longjun Liu; Chao Li 009; Hongbin Sun 001; Yang Hu 001; Jingmin Xin; Nanning Zheng 001; Tao Li 006 (IEEE Comput. Archit. Lett., 2015)

Bridging the Semantic Gaps of GPU Acceleration for Scale-out CNN-based Big Data Processing: Think Big, See Small. - Mingcong Song; Yang Hu 001; Yunlong Xu; Chao Li 009; Huixiang Chen 001; Jingling Yuan; Tao Li 006 (PACT, 2016)

HOPE: Enabling Efficient Service Orchestration in Software-Defined Data Centers. - Yang Hu 001; Chao Li 009; Longjun Liu; Tao Li 006 (ICS, 2016)

Towards an Adaptive Multi-Power-Source Datacenter. - Longjun Liu; Hongbin Sun 001; Chao Li 009; Yang Hu 001; Nanning Zheng 001; Tao Li 006 (ICS, 2016)

Towards efficient server architecture for virtualized network function deployment: Implications and implementations. - Yang Hu 001; Tao Li 006 (MICRO, 2016)

RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters. - Longjun Liu; Hongbin Sun 001; Chao Li 009; Yang Hu 001; Jingmin Xin; Nanning Zheng 001; Tao Li 006 (J. Supercomput., 2016)

Towards "Full Containerization" in Containerized Network Function Virtualization. - Yang Hu 001; Mingcong Song; Tao Li 006 (ASPLOS, 2017)

Towards Pervasive and User Satisfactory CNN across GPU Microarchitectures. - Mingcong Song; Yang Hu 001; Huixiang Chen 001; Tao Li 006 (HPCA, 2017)

GaaS workload characterization under NUMA architecture for virtualized GPU. - Huixiang Chen 001; Meng Wang; Yang Hu 001; Mingcong Song; Tao Li 006 (ISPASS, 2017)

LocoFS: a loosely-coupled metadata service for distributed file systems. - Siyang Li; Youyou Lu; Jiwu Shu; Yang Hu 001; Tao Li 006 (SC, 2017)

Oasis: Scaling Out Datacenter Sustainably and Economically. - Chao Li 009; Yang Hu 001; Juncheng Gu; Jingling Yuan; Tao Li 006 (IEEE Trans. Parallel Distributed Syst., 2017)

Enabling Efficient Network Service Function Chain Deployment on Heterogeneous Server Platform. - Yang Hu 001; Tao Li 006 (HPCA, 2018)

In-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems. - Mingcong Song; Kan Zhong; Jiaqi Zhang 002; Yang Hu 001; Duo Liu; Weigong Zhang; Jing Wang 055; Tao Li 006 (HPCA, 2018)

Prediction Based Execution on Deep Neural Networks. - Mingcong Song; Jiechen Zhao 003; Yang Hu 001; Jiaqi Zhang 002; Tao Li 006 (ISCA, 2018)

A Flattened Metadata Service for Distributed File Systems. - Siyang Li; Fenlin Liu; Jiwu Shu; Youyou Lu; Tao Li 006; Yang Hu 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Exploring Customizable Heterogeneous Power Distribution and Management for Datacenter. - Longjun Liu; Hongbin Sun 001; Chao Li 009; Yang Hu 001; Tao Li 006; Nanning Zheng 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Architectural and Cost Implications of the 5G Edge NFV Systems. - Yang Hu 001; Jianda Wang (ICCD, 2019)

An FPGA Implementation of Stochastic Computing-Based LSTM. - Guy Maor; Xiaoming Zeng; Zhendong Wang; Yang Hu 001 (ICCD, 2019)

Characterizing and orchestrating NFV-ready servers for efficient edge data processing. - Lu Zhang 049; Chao Li 009; Pengyu Wang 003; Yunxin Liu 001; Yang Hu 001; Quan Chen 002; Minyi Guo (IWQoS, 2019)

Characterizing and Understanding the Architectural Implications of Cloudnative Edge NFV Workloads. - Jianda Wang; Yang Hu 001 (NFV-SDN, 2019)

Understanding and Tackling the Hidden Memory Latency for Edge-based Heterogeneous Platform. - Zhendong Wang; Zhen Wang 019; Cong Liu 005; Yang Hu 001 (HotEdge, 2020)

Performance Analysis of 5G NR vRAN Platform and its Implications on Edge Computing. - Jianda Wang; Yang Hu 001 (ISPASS, 2020)

Co-Optimizing Performance and Memory Footprint Via Integrated CPU/GPU Memory Management, an Implementation on Autonomous Driving Platform. - Soroush Bateni; Zhendong Wang; Yuankun Zhu; Yang Hu 001; Cong Liu 005 (RTAS, 2020)

ANT-man: towards agile power management in the microservice era. - Xiaofeng Hou; Chao Li 009; Jiacheng Liu 001; Lu Zhang 049; Yang Hu 001; Minyi Guo (SC, 2020)

Co-Optimizing Performance and Memory FootprintVia Integrated CPU/GPU Memory Management, anImplementation on Autonomous Driving Platform. - Soroush Bateni; Zhendong Wang; Yuankun Zhu; Yang Hu 001; Cong Liu 005 (CoRR, 2020)

A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics. - Liwei Zhou; Yang Hu 001; Yiorgos Makris (IEEE Trans. Computers, 2020)

Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform. - Zhendong Wang; Zihang Jiang; Zhen Wang 019; Xulong Tang; Cong Liu 005; Shouyi Yin; Yang Hu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Q-VR: system-level design for future mobile collaborative virtual reality. - Chenhao Xie 001; Xie Li; Yang Hu 001; Huwan Peng; Michael B. Taylor; Shuaiwen Leon Song (ASPLOS, 2021)

Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption. - Zhendong Wang; Rujia Wang; Zihang Jiang; Xulong Tang; Shouyi Yin; Yang Hu 001 (ATS, 2021)

Characterization and Implication of Edge WebAssembly Runtimes. - Zhen Wang 019; Jianda Wang; Zhendong Wang; Yang Hu 001 (HPCC/DSS/SmartCity/DependSys, 2021)

Enabling Efficient SIMD Acceleration for Virtual Radio Access Network. - Jianda Wang; Yang Hu 001 (ICPP, 2021)

Tackling Variabilities in Autonomous Driving. - Yuqiong Qi; Yang Hu 001; Haibin Wu; Shen Li; Haiyu Mao; Xiaochun Ye; Dongrui Fan; Ninghui Sun (CoRR, 2021)

Enabling efficient deep convolutional neural network-based sensor fusion for autonomous driving. - Xiaoming Zeng; Zhendong Wang; Yang Hu 001 (DAC, 2022)

Brief Industry Paper: The Necessity of Adaptive Data Fusion in Infrastructure-Augmented Autonomous Driving System. - Shaoshan Liu; Jianda Wang; Zhendong Wang; Bo Yu 014; Wei Hu; Yahui Liu; Jie Tang 003; Shuaiwen Leon Song; Cong Liu 005; Yang Hu 001 (RTAS, 2022)

A synergistic reinforcement learning-based framework design in driving automation. - Yuqiong Qi; Yang Hu 001; Haibin Wu; Shen Li; Xiaochun Ye; Dongrui Fan (Comput. Electr. Eng., 2022)

Towards a High-performance and Secure Memory System and Architecture for Emerging Applications. - Zhendong Wang; Yang Hu 001 (CoRR, 2022)

Demystifying Arch-hints for Model Extraction: An Attack in Unified Memory System. - Zhendong Wang; Xiaoming Zeng; Xulong Tang; Danfeng Zhang; Xing Hu; Yang Hu 001 (CoRR, 2022)

Towards Efficient Architecture and Algorithms for Sensor Fusion. - Zhendong Wang; Xiaoming Zeng; Shuaiwen Leon Song; Yang Hu 001 (CoRR, 2022)

A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions. - Xiaofeng Chen; Ruiqi Guo; Zhiheng Yue; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2023)

CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering. - Ruiqi Guo; Yang Wang 089; Xiaofeng Chen; Lei Wang; Hao Sun; Jingchuan Wei; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (A-SSCC, 2023)

A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. - Yubin Qin; Yang Wang 089; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Yang Zhou; Yuanqi Fan; Jingchuan Wei; Tianbao Chen; Leibo Liu; Shaojun Wei; Yang Hu 001; et al. (A-SSCC, 2023)

RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. - Qidie Wu; Jiangyuan Gu; Youxu Lin; Boxiao Han; Hongjun He; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2023)

FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. - Yubin Qin; Yang Wang 089; Dazheng Deng; Zhiren Zhao; Xiaolong Yang; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2023)

MuITCIM: A 28nm $2.24 mu mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Yabing Wang; Ruiqi Guo; Limei Tang; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2023)

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Boxiao Han; Hongjun He; Fengbin Tu; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (MICRO, 2023)

A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. - Yang Wang 089; Yubin Qin; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2023)

Catch-Up Distillation: You Only Need to Train Once for Accelerating Sampling. - Shitong Shao; Xu Dai; Shouyi Yin; Lujun Li 001; Huanran Chen; Yang Hu 001 (CoRR, 2023)

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Fengbin Tu; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (CoRR, 2023)

WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. - Haojia Hui; Jiangyuan Gu; Xunbo Hu; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (CoRR, 2023)

Wafer-scale Computing: Advancements, Challenges, and Future Perspectives. - Yang Hu 001; Xinhan Lin; Huizheng Wang; Zhen He; Xingmao Yu; Jiahao Zhang; Qize Yang; Zheng Xu; Sihan Guan; Jiahao Fang; Haoran Shang; Xinru Tang; et al. (CoRR, 2023)

STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. - Weiwei Wu; Fengbin Tu; Mengqi Niu; Zhiheng Yue; Leibo Liu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Towards an Efficient SIMD Virtual Radio Access Network (vRAN) and Edge Cloud System. - Jianda Wang; Zhen Wang 019; Yang Hu 001 (IEEE Trans. Cloud Comput., 2023)

Data Fusion in Infrastructure-Augmented Autonomous Driving System: Why? Where? and How? - Jianda Wang; Zhendong Wang; Bo Yu 014; Jie Tang 003; Shuaiwen Leon Song; Cong Liu 005; Yang Hu 001 (IEEE Internet Things J., 2023)

A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (A-SSCC, 2024)

Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Yuxuan Li; Liuxin Lv; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference. - Zheng Xu; Xu Dai; Shaojun Wei; Shouyi Yin; Yang Hu 001 (DAC, 2024)

FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. - Xiaolong Yang; Yang Wang 089; Yubin Qin; Jiachen Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. - Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things. - Xiaofeng Hou; Tongqiao Xu; Chao Li 009; Cheng Xu; Jiacheng Liu 001; Yang Hu 001; Jieru Zhao; Jingwen Leng; Kwang-Ting Cheng; Minyi Guo (ISCA, 2024)

MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. - Yubin Qin; Yang Wang 089; Zhiren Zhao; Xiaolong Yang; Yang Zhou; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2024)

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. - Zhiheng Yue; Huizheng Wang; Jiahao Fang; Jinyi Deng; Guangyang Lu; Fengbin Tu; Ruiqi Guo; Yuxuan Li; Yubin Qin; Yang Wang 089; Chao Li 009; Huiming Han; et al. (ISCA, 2024)

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. - Ruiqi Guo; Lei Wang; Xiaofeng Chen; Hao Sun; Zhiheng Yue; Yubin Qin; Huiming Han; Yang Wang 089; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. - Zhiheng Yue; Xujiang Xiang; Fengbin Tu; Yang Wang 089; Yiming Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qinze Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (MICRO, 2024)

Boosting Data Center Performance via Intelligently Managed Multi-backend Disaggregated Memory. - Jing Wang 055; Hanzhang Yang; Chao Li 009; Yiming Zhuansun; Wang Yuan; Cheng Xu; Xiaofeng Hou; Minyi Guo; Yang Hu 001; Yaqian Zhao (SC, 2024)

ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. - Yiqi Wang 005; Zhen He; Chenggang Zhao; Zihan Wu 006; Mingyu Gao 001; Huiming Han; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation. - Ruiqi Guo; Xiaofeng Chen; Lei Wang; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. - Yubin Qin; Yang Wang 089; Xiaolong Yang; Zhiren Zhao; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture. - Jinyi Deng; Xinru Tang; Zhiheng Yue; Guangyang Lu; Qize Yang; Jiahao Zhang; Jinxi Li; Chao Li 009; Shaojun Wei; Yang Hu 001; Shouyi Yin (CoRR, 2024)

PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training. - Jiahao Fang; Huizheng Wang; Qize Yang; Dehao Kong; Xu Dai; Jinyi Deng; Yang Hu 001; Shouyi Yin (CoRR, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qize Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (CoRR, 2024)

Tackling the Dynamicity in a Production LLM Serving System with SOTA Optimizations via Hybrid Prefill/Decode/Verify Scheduling on Efficient Meta-kernels. - Mingcong Song; Xinru Tang; Fengfan Hou; Jing Li; Wei Wei; Yipeng Ma; Runqiu Xiao; Hongjie Si; Dingcheng Jiang; Shouyi Yin; Yang Hu 001; Guoping Long (CoRR, 2024)

Optimizing the Micro-Architectural Performance of the Current and Emerging Edge Infrastructure. - Jianda Wang; Zhen Wang 019; Weili Wu 001; Yang Hu 001 (IEEE Trans. Cloud Comput., 2024)

MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2024)

CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering. - Ruiqi Guo; Xiaofeng Chen; Lei Wang; Yang Wang 089; Hao Sun; Jingchuan Wei; Huiming Han; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2024)

Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow. - Yubin Qin; Yang Wang 089; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Yang Zhou; Yuanqi Fan; Jingchuan Wei; Tianbao Chen; Leibo Liu; Shaojun Wei; Yang Hu 001; et al. (IEEE J. Solid State Circuits, 2024)

PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture. - Weiwei Wu; Fengbin Tu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (ASAP, 2025)

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. - Zhen He; Yiqi Wang 005; Zihan Wu 006; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (HPCA, 2025)

WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips. - Zheng Xu; Dehao Kong; Jiaxin Liu; Jinxi Li; Jingxiang Hou; Xu Dai; Chao Li 009; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2025)

PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. - Qize Yang; Taiquan Wei; Sihan Guan; Chengran Li; Haoran Shang; Jinyi Deng; Huizheng Wang; Chao Li 009; Lei Wang; Yan Zhang; Shouyi Yin; Yang Hu 001 (ISCA, 2025)

Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip. - Xingmao Yu; Dingcheng Jiang; Jinyi Deng; Jingyao Liu; Chao Li 009; Shouyi Yin; Yang Hu 001 (ISCA, 2025)

23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation. - Yubin Qin; Yang Wang 089; Jiachen Wang; Zhiwei Lin; Yushu Zhao; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <-30 Loss for Compound AI. - Zhiheng Yue; Xujiang Xiang; Yang Wang 089; Ruiqi Guo; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Computers, 2025)

TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. - Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Fengbin Tu; Shouyi Yin (IEEE J. Solid State Circuits, 2025)

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Ruiqi Guo; Fengbin Tu; Jianxun Yang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)

BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training. - Yang Zhou; Yang Wang 089; Wenxin Yin; Yazheng Jiang; Jingchuan Wei; Yubin Qin; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Xiaolong Zhang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

HPCTransCompile: An AI Compiler Generated Dataset for High-Performance CUDA Transpilation and LLM Preliminary Exploration. - Jiaqi Lv; Xufeng He; Yanchen Liu; Xu Dai; Yang Hu 001; Shouyi Yin (CoRR, 2025)

An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)