Yang Jiang

According to our database1, Yang Jiang authored at least 12 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density.
IEEE J. Solid State Circuits, 2019

A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters.
IEEE J. Solid State Circuits, 2018

A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm<sup>2</sup>.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2013
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
An ELD tracking compensation technique for active-RC CT ΣΔ modulators.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010
A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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