Yang Li

Affiliations:
  • University of Electro-Communications, Department of Informatics, Tokyo, Japan


According to our database1, Yang Li authored at least 44 papers between 2009 and 2024.

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Bibliography

2024
All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023
Software Evaluation for Second Round Candidates in NIST Lightweight Cryptography.
J. Inf. Process., 2023

Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
Mixture-Based 5-Round Physical Attack against AES: Attack Proposal and Noise Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Optimized Software Implementations of Ascon, Grain-128AEAD, and TinyJambu on ARM Cortex-M0.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

2021
Revisiting System Noise in Side-Channel Attacks: Mutual Assistant SCA vs. Genetic Algorithm.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
A Framework for Evaluation and Analysis on Infection Countermeasures Against Fault Attacks.
IEEE Trans. Inf. Forensics Secur., 2020

Signal Injection Attack on Time-to-Digital Converter and Its Application to Physically Unclonable Function.
IACR Cryptol. ePrint Arch., 2020

(Short Paper) Signal Injection Attack on Time-to-Digital Converter and Its Application to Physically Unclonable Function.
Proceedings of the Advances in Information and Computer Security, 2020

A Key Recovery Algorithm Using Random Key Leakage from AES Key Schedule.
Proceedings of the International Symposium on Information Theory and Its Applications, 2020

An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

Simple Electromagnetic Analysis Against Activation Functions of Deep Neural Networks.
Proceedings of the Applied Cryptography and Network Security Workshops, 2020

2019
Side-Channel Leakage of Alarm Signal for a Bulk-Current-Based Laser Sensor.
Proceedings of the Information Security and Cryptology - 15th International Conference, 2019

2018
Recovering Memory Access Sequence with Differential Flush+Reload Attack.
Proceedings of the Information Security Practice and Experience, 2018

Improved Differential Fault Analysis on Authenticated Encryption of PAEQ-128.
Proceedings of the Information Security and Cryptology - 14th International Conference, 2018

2015
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Security of Block Ciphers - From Algorithm Design to Hardware Implementation.
Wiley, ISBN: 978-1-118-66001-0, 2015

2014
Practical DFA Strategy for AES Under Limited-access Conditions.
J. Inf. Process., 2014

Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014

Single-Chip Implementation and Evaluation of Passive UHF RFID Tag with Hash-Based Mutual Authentication.
Proceedings of the Radio Frequency Identification System Security, 2014

2013
A New Type of Fault-Based Attack: Fault Behavior Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Yet Another Fault-Based Leakage in Non-uniform Faulty Ciphertexts.
Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013

Coupon Collector's Problem for Fault Analysis against AES - High Tolerance for Noisy Fault Injections.
Proceedings of the Financial Cryptography and Data Security, 2013

Exploring the Relations between Fault Sensitivity and Power Consumption.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2013

2012
Fault Injection and Key Retrieval Experiments on an Evaluation Board.
Proceedings of the Fault Analysis in Cryptography, 2012

Information-Theoretic Approach to Optimal Differential Fault Analysis.
IEEE Trans. Inf. Forensics Secur., 2012

New Fault-Based Side-Channel Attack Using Fault Sensitivity.
IEEE Trans. Inf. Forensics Secur., 2012

Toward Effective Countermeasures against an Improved Fault Sensitivity Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Key-Dependent Weakness of AES-Based Ciphers under Clockwise Collision Distinguisher.
Proceedings of the Information Security and Cryptology - ICISC 2012, 2012

An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks.
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

An Extension of Fault Sensitivity Analysis Based on Clockwise Collision.
Proceedings of the Information Security and Cryptology - 8th International Conference, 2012

2011
Power Analysis against a DPA-Resistant S-Box Implementation Based on the Fourier Transform.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Clockwise Collision Analysis - Overlooked Side-Channel Leakage Inside Your Measurements.
IACR Cryptol. ePrint Arch., 2011

Revisit fault sensitivity analysis on WDDL-AES.
Proceedings of the HOST 2011, 2011

Fault Sensitivity Analysis Against Elliptic Curve Cryptosystems.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
An Information Theoretic Perspective on the Differential Fault Analysis against AES.
IACR Cryptol. ePrint Arch., 2010

Efficient Differential Fault Analysis for AES.
IACR Cryptol. ePrint Arch., 2010

Combination of SW Countermeasure and CPU Modification on FPGA against Power Analysis.
Proceedings of the Information Security Applications - 11th International Workshop, 2010

Power Variance Analysis breaks a masked ASIC implementation of AES.
Proceedings of the Design, Automation and Test in Europe, 2010

Fault Sensitivity Analysis.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

Non-full-active Super-Sbox Analysis: Applications to ECHO and Grøstl.
Proceedings of the Advances in Cryptology - ASIACRYPT 2010, 2010

2009
Security Evaluation of a DPA-Resistant S-Box Based on the Fourier Transform.
Proceedings of the Information and Communications Security, 11th International Conference, 2009


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