Low Power Trellis Decoder with Overscaled Supply Voltage. - Yang Liu 016; Tong Zhang 002; Jiang Hu (SiPS, 2006)

On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing. - Yang Liu 016; Tong Zhang 002 (ISLPED, 2007)

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. - Yang Liu 016; Tong Zhang 002; Jiang Hu (ISQED, 2007)

Analysis of voltage overscaled computer arithmetics in low power signal processing systems. - Yang Liu 016; Tong Zhang 002; Keshab K. Parhi (ACSCC, 2008)

Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling. - Yang Liu 016; Fei Sun; Tong Zhang 002 (ISCAS, 2008)

Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. - Yang Liu 016; Tong Zhang 002; Jiang Hu (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration. - Yang Liu 016; Jibang Liu; Tong Zhang 002 (ISQED, 2010)

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators. - Yiran Li 001; Yang Liu 016; Tong Zhang 002 (Signal Process. Image Commun., 2010)

Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage. - Yang Liu 016; Tong Zhang 002; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2010)