A process variation insensitive bandgap reference with self-calibration technique. - Ling Du; Ning Ning 002; Kejun Wu; Yang Liu 062; Qi Yu 002 (ASICON, 2013)

Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure. - Zhentao Xu; X. L. Zhang; J. Z. Chen; Shaogang Hu; Qi Yu 002; Yang Liu 062; Wei Meng Lim (J. Circuits Syst. Comput., 2013)

A 10-bit 100MS/s subrange SAR ADC with time-domain quantization. - Ling Du; Shuangyi Wu; Min Jiang; Ning Ning 002; Qi Yu 002; Yang Liu 062 (ISCAS, 2014)

A digital background calibration technique for SAR ADC based on capacitor swapping. - Ling Du; Ning Ning 002; Shuangyi Wu; Qi Yu 002; Yang Liu 062 (IEICE Electron. Express, 2014)

Digital Background Calibration for Timing skew in Time-Interleaved ADC. - Jing Li 022; Yang Liu 062; Shuangyi Wu; Ning Ning 002; Qi Yu 002 (J. Circuits Syst. Comput., 2014)

A dithering Technique for Sha_less Pipelined ADC. - Ning Ning 002; Ling Du; Hua Chen; Shuangyi Wu; Qi Yu 002; Yang Liu 062 (J. Circuits Syst. Comput., 2014)

A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs. - Jing Li 022; Shuangyi Wu; Yang Liu 062; Ning Ning 002; Qi Yu 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Total ionizing dose sensitivity of function blocks in FRAM. - Ke Gu; Juin J. Liou; Wei Li; Yang Liu 062; Ping Li 014 (Microelectron. Reliab., 2015)

A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors. - Zhentao Xu; Wei Wang 152; Ning Ning 002; Wei Meng Lim; Yang Liu 062; Qi Yu 002 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network. - Deyu Kong; Shaogang Hu; Yuancong Wu; Junjie Wang 008; Canlong Xiong; Qi Yu 002; Zhengyu Shi; Zhen Liu 013; Tupei Chen; You Yin; Sumio Hosaka; Yang Liu 062 (IEEE Access, 2018)

The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction. - Jian Luo 004; Jing Li 022; Ning Ning 002; Yang Liu 062; Qi Yu 002 (IEEE Access, 2018)

Predicting House Price With a Memristor-Based Artificial Neural Network. - Junjie Wang 008; Shaogang Hu; X. T. Zhan; Q. Luo; Qi Yu 002; Zhen Liu 013; Tupei Chen; Y. Yin; Sumio Hosaka; Yang Liu 062 (IEEE Access, 2018)

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS. - Jian Luo 004; Jing Li 022; Ning Ning 002; Yang Liu 062; Qi Yu 002 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC. - Jian Luo 004; Jing Li 022; Ning Ning 002; Kejun Wu; Zhen Liu 013; Yang Liu 062; Qi Yu 002 (ISCAS, 2019)

Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range. - Rui Guo; Kun Qian; Jinping Wei; Tupei Chen; Yanchen Liu; Deyu Kong; Junjie Wang 008; Yuancong Wu; Shaogang Hu; Qi Yu 002; Yang Liu 062 (IEEE Access, 2019)

Study of Recall Time of Associative Memory in a Memristive Hopfield Neural Network. - Deyu Kong; Shaogang Hu; Junjie Wang 008; Zhen Liu 013; Tupei Chen; Qi Yu 002; Yang Liu 062 (IEEE Access, 2019)

Implementation of a Low Noise Amplifier With Self-Recovery Capability. - Yanchen Liu; Caizhi Zhang; Tupei Chen; Deyu Kong; Rui Guo; Junjie Wang 008; Yuancong Wu; Shaogang Hu; L. M. Rong; Qi Yu 002; Yang Liu 062 (IEEE Access, 2019)

A Neuromorphic-Hardware Oriented Bio-Plausible Online-Learning Spiking Neural Network Model. - Chunming Qiao; Shaogang Hu; Junjie Wang 008; C. M. Zhang; Tupei Chen; Ning Ning 002; Qi Yu 002; Yang Liu 062 (IEEE Access, 2019)

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters. - Jian Luo 004; Jing Li 022; Shuangyi Wu; Ning Ning 002; Yang Liu 062 (J. Circuits Syst. Comput., 2019)

Design of AM Self-Capacitive Transparent Touch Panel Based on a-IGZO Thin-Film Transistors. - Kejun Wu; Jun Zhang 055; Yuanbo Li; Xiangzhan Wang; Yang Liu 062; Qi Yu 002; Tupei Chen (IEEE Access, 2020)

An energy-efficient deep convolutional neural networks coprocessor for multi-object detection. - Yuancong Wu; Junjie Wang 008; Kun Qian; Yanchen Liu; Rui Guo; Shaogang Hu; Qi Yu 002; Tupei Chen; Yang Liu 062; Limei Rong (Microelectron. J., 2020)

Application of Deep Compression Technique in Spiking Neural Network Chip. - Yanchen Liu; Kun Qian; Shaogang Hu; Kun An; Sheng Xu; Xitong Zhan; Junjie Wang 008; Rui Guo; Yuancong Wu; Tupei Chen; Qi Yu 002; Yang Liu 062 (IEEE Trans. Biomed. Circuits Syst., 2020)

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC. - Jian Luo 004; Yang Liu 062; Jing Li 022; Ning Ning 002; Kejun Wu; Zhen Liu 013; Qi Yu 002 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Design of a constant loop bandwidth phase-locked loop based on artificial neural network. - Rui Guo; Yuancong Wu; Shaogang Hu; Qi Yu 002; Tupei Chen; Yang Liu 062 (IEICE Electron. Express, 2021)

2022 roadmap on neuromorphic devices and applications research in China. - Qing Wan; Changjin Wan; Huaqiang Wu; Yuchao Yang 001; Xiaohe Huang; Peng Zhou 021; Lin Chen; Tian-Yu Wang; Yi Li 049; Kanhao Xue; Yu-Hui He; Xiangshui Miao; et al. (Neuromorph. Comput. Eng., 2022)

A Co-Designed Neuromorphic Chip With Compact (17.9K F2) and Weak Neuron Number-Dependent Neuron/Synapse Modules. - Shaogang Hu; Guanchao Qiao; X. K. Liu; Y. H. Liu; C. M. Zhang; Yue Zuo; Pujun Zhou; Yian Liu 001; Ning Ning 002; Qi Yu 002; Yang Liu 062 (IEEE Trans. Biomed. Circuits Syst., 2022)

A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology. - Yihe Liu; Junjie Wang 008; Shuang Liu 007; Mingyuan Sun; Kai Tang; Guohui Ren; Xindi Zhao; Mingliang Sun; Yang Liu 062 (CECCT, 2023)

FPGA-implemented Memristor-based Transient Chaotic Neural Network for AES Edge Encryption. - Hongzhe Wang; Kunsong Liu; Yi'an Liu 001; Junjie Wang 008; Mingyuan Sun; Kai Tang; Guohui Ren; Xindi Zhao; Yang Liu 062 (CECCT, 2023)

An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning. - Shuang Liu 007; Junjie Wang 008; Jingtao Zhou; Shaogang Hu; Qi Yu 002; Tupei Chen; Yang Liu 062 (IEEE Trans. Biomed. Circuits Syst., 2023)

Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory. - Hongzhe Wang; Junjie Wang 008; Hao Hu; Guo Li; Shaogang Hu; Qi Yu 002; Zhen Liu 013; Tupei Chen; Shijie Zhou; Yang Liu 062 (Sensors, 2023)

An efficient pruning and fine-tuning method for deep spiking neural network. - Liwei Meng; Guanchao Qiao; Xiaoyang Zhang; Jian Bai; Yue Zuo; Pujun Zhou; Yang Liu 062; Shaogang Hu (Appl. Intell., 2023)

Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth. - Pujun Zhou; Yue Zuo; Guanchao Qiao; C. M. Zhang; Zhong Zhang 002; Liwei Meng; Qi Yu 002; Yang Liu 062; Shaogang Hu (IEEE Trans. Biomed. Circuits Syst., 2023)

A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network. - Ruichen Ma; Guanchao Qiao; Yian Liu 001; Liwei Meng; Ning Ning 002; Yang Liu 062; Shaogang Hu (CVPR, 2024)

Live Demonstration for Input-Sparsity-Aware RRAM Processing-in-Memory Chip. - Junjie Wang 008; Shuang Liu 007; Ruicheng Pan; Shiqin Yan; Yihe Liu; Yang Liu 062 (ISCAS, 2024)

Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network. - Yihe Liu; Junjie Wang 008; Shuang Liu 007; Mingyuan Sun; Xiaoyang Zhang; Jingtao Zhou; Shiqin Yan; Ruicheng Pan; Hao Hu; Yang Liu 062 (Microelectron. J., 2024)

Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip. - Junjie Wang 008; Teng Zhang; Shuang Liu 007; Yihe Liu; Yuancong Wu; Shaogang Hu; Tupei Chen; Yang Liu 062; Yuchao Yang 001; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

Fullerene-Inspired Efficient Neuromorphic Network-on-Chip Scheme. - Pujun Zhou; Qi Yu 002; M. Chen; Guanchao Qiao; Yue Zuo; Zhong Zhang 002; Yang Liu 062; Shaogang Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks. - Yue Zuo; Ning Ning 002; Guanchao Qiao; J. H. Wu; Junhan Bao; Xiaoyang Zhang; Jian Bai; F. H. Wu; Yang Liu 062; Qi Yu 002; Shaogang Hu (IEEE Trans. Biomed. Circuits Syst., 2024)

Spatio-Temporal Fusion Spiking Neural Network for Frame-Based and Event-Based Camera Sensor Fusion. - Guanchao Qiao; Ning Ning 002; Yue Zuo; Pujun Zhou; Mingliang Sun; Shaogang Hu; Qi Yu 002; Yang Liu 062 (IEEE Trans. Emerg. Top. Comput. Intell., 2024)

An Image Encryption Algorithm Based on HNN with Memristor. - Yian Liu 001; Hao Hu; Ya Gao; Shaogang Hu; Qi Yu 002; Tupei Chen; Yang Liu 062 (Int. J. Bifurc. Chaos, 2025)

A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing. - Pujun Zhou; R. C. Ma; Y. C. Chen; Z. T. Liu; C. Y. Liu; Liwei Meng; Guanchao Qiao; Yang Liu 062; Qi Yu 002; Shaogang Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)