Efficient In-Memory Processing Using Spintronics. - Zamshed I. Chowdhury; Jonathan D. Harms; S. Karen Khatamifard; Masoud Zabihi; Yang Lv 003; Andrew Lyle; Sachin S. Sapatnekar; Ulya R. Karpuzcu; Jianping Wang 006 (IEEE Comput. Archit. Lett., 2018)

Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions. - Yang Lv 003; Robert P. Bloom; Jianping Wang 006 (CoRR, 2019)

Error Detection and Correction for Processing in Memory (PiM). - M. Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Masoud Zabihi; Yang Lv 003; Brandon Zink; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2022)

Experimental demonstration of magnetic tunnel junction-based computational random-access memory. - Yang Lv 003; Brandon R. Zink; Robert P. Bloom; M. Hüsrev Cilasun; Pravin Khanal; Salonik Resch; Zamshed I. Chowdhury; Ali Habiboglu; Weigang Wang; Sachin S. Sapatnekar; Ulya R. Karpuczu; Jianping Wang 006 (CoRR, 2023)

On Gate Flip Errors in Computing-In-Memory. - Zamshed I. Chowdhury; Hüsrev Cilasun; Salonik Resch; Masoud Zabihi; Yang Lv 003; Brandon Zink; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (DATE, 2024)

On Error Correction for Nonvolatile Processing-In-Memory. - Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Masoud Zabihi; Yang Lv 003; Brandon Zink; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ISCA, 2024)

The Case for Secure Miniservers Beyond the Edge. - Salonik Resch; Hüsrev Cilasun; Zamshed I. Chowdhury; Masoud Zabihi; Yang Lv 003; Jianping Wang 006; Sachin S. Sapatnekar; Ismail Akturk; Ulya R. Karpuzcu (IEEE Trans. Computers, 2025)

CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation. - Sohan Salahuddin Mugdho; Md. Shahedul Hasan; Brahmdutta Dixit; Yang Lv 003; Jian-Ping Wang 006; Cheng Wang 036 (ACM Great Lakes Symposium on VLSI, 2026)