Research on Modeling Traversing Features in Concurrent Software System. - Yang Su 003; Xuan-Wu Zhou; Min-Qing Zhang (CSSE (2), 2008)

Approach on Aspect-Oriented Software Reverse Engineering at Requirements Level. - Yang Su 003; Xuan-Wu Zhou; Min-Qing Zhang (CSSE (2), 2008)

Further Study on Proxy Authorization and Its Scheme. - Xuanwu Zhou; Yang Su 003; Ping Wei 005 (Complex (2), 2009)

A high security and efficiency protection of confidentiality and integrity for off-chip memory. - Yang Su 003; Junwei Shen; Min-Qing Zhang (J. Ambient Intell. Humaniz. Comput., 2019)

A Survey of Personalized Recommendation Based on Machine Learning Algorithms. - Luogeng Tian; Bailong Yang; Xinli Yin; Yang Su 003 (EITCE, 2020)

FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption. - Yang Su 003; Bailong Yang; Chen Yang 005; Luogeng Tian (IEEE Access, 2020)

A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference. - Chen Yang 005; Zepeng Yang; Jia Hou; Yang Su 003 (ICECS, 2021)

High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor. - Yang Su 003; Bai-Long Yang; Chen Yang 005; Jing-Yuan He (J. Ambient Intell. Humaniz. Comput., 2021)

ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation. - Yang Su 003; Bai-Long Yang; Chen Yang 005; Songyin Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. - Yang Su 003; Bai-Long Yang; Chen Yang 005; Zepeng Yang; Yi-Wei Liu (IEEE Trans. Very Large Scale Integr. Syst., 2022)

TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Yang Su 003 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Sitting Posture Recognition Based on the Computer's Camera. - Songyin Zhao; Yang Su 003 (CVIPPR, 2024)

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Jia Hou; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography. - Yushu Yang; Zihang Wang; Jianfei Wang 003; Jia Hou; Yang Su 003; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (ASP-DAC, 2025)

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. - Jianfei Wang 003; Chen Yang 005; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Leibo Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. - Zihang Wang; Yushu Yang; Jianfei Wang 003; Jia Hou; Yang Su 003; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. - Jianfei Wang 003; Chen Yang 005; Yishuo Meng; Fahong Zhang 002; Jia Hou; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. - Jia Hou; Jianfei Wang 003; Yishuo Meng; Fahong Zhang 002; Yang Su 003; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)