Yang Zhang

According to our database1, Yang Zhang authored at least 9 papers between 2017 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A 0.032-mm<sup>2</sup> 43.3-fJ/Step 100-200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters.
IEEE J. Solid State Circuits, 2020

2019
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Extremely Linear Multi-Level DAC for Continuous-Time Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback.
IEICE Electron. Express, 2019

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators.
IEEE Access, 2019

2018
Improving Power Efficiency for Active-RC Delta-Sigma Modulators Using a Passive-RC Low-Pass Filter in the Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network.
Proceedings of the International SoC Design Conference, 2017


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