A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability. - Yang Zhang 051; Dan Feng 001; Jingning Liu; Wei Tong 001; Bing Wu 001; Caihua Fang (DAC, 2017)

DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory. - Chengning Wang; Dan Feng 001; Jingning Liu; Wei Tong 001; Bing Wu 001; Yang Zhang 051 (ICCD, 2017)

Aliens: a novel hybrid architecture for resistive random-access memory. - Bing Wu 001; Dan Feng 001; Wei Tong 001; Jingning Liu; Shuai Li; Mingshun Yang; Chengning Wang; Yang Zhang 051 (ICCAD, 2018)

Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive Memory Architecture. - Yang Zhang 051; Dan Feng 001; Zhipeng Tan; Jingning Liu; Wei Tong 001; Chengning Wang (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

CACF: A Novel Circuit Architecture Co-optimization Framework for Improving Performance, Reliability and Energy of ReRAM-based Main Memory System. - Yang Zhang 051; Dan Feng 001; Wei Tong 001; Yu Hua 001; Jingning Liu; Zhipeng Tan; Chengning Wang; Bing Wu 001; Zheng Li 005; Gaoxiang Xu (ACM Trans. Archit. Code Optim., 2018)

Tiered-ReRAM: A Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture. - Yang Zhang 051; Dan Feng 001; Wei Tong 001; Jingning Liu; Chengning Wang; Jie Xu 013 (MSST, 2019)

FvRS: Efficiently identifying performance-critical data for improving performance of big data processing. - Gaoxiang Xu; Zhipeng Tan; Dan Feng 001; Laurence T. Yang; Wei Zhou 013; Xinyan Zhang; Yang Zhang 051; Jie Xu 013 (Future Gener. Comput. Syst., 2019)

Cross-point Resistive Memory: Nonideal Properties and Solutions. - Chengning Wang; Dan Feng 001; Wei Tong 001; Jingning Liu; Zheng Li 005; Jiayi Chang; Yang Zhang 051; Bing Wu 001; Jie Xu 013; Wei Zhao 034; Yilin Li; Ruoxi Ren (ACM Trans. Design Autom. Electr. Syst., 2019)

A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches. - Bing Wu 001; Dan Feng 001; Wei Tong 001; Jingning Liu; Chengning Wang; Wei Zhao 034; Yang Zhang 051 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture. - Yang Zhang 051; Zhibin Yu 001; Liang Gu; Chengning Wang; Dan Feng 001 (IEEE Access, 2021)

Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage. - Chengning Wang; Dan Feng 001; Wei Tong 001; Jingning Liu; Bing Wu 001; Wei Zhao 034; Yang Zhang 051; Yiran Chen 001 (IEEE Trans. Computers, 2021)

Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory. - Chengning Wang; Dan Feng 001; Wei Tong 001; Yu Hua 001; Jingning Liu; Bing Wu 001; Wei Zhao 034; Linghao Song; Yang Zhang 051; Jie Xu 013; Xueliang Wei; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)