Robot navigation based on pseudo-binocular stereo vision and linear fitting. - Huanshihong Deng; Pingcheng Dong; Zhuoao Li; Haoran Lyu; Yangyi Zhang 002; Yiwei Luo; Fengwei An (ICTA, 2020)

A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching. - Pingcheng Dong; Zhuoao Li; Zhuoyu Chen; Ruoheng Yao; Huanshihong Deng; Wenyue Zhang; Yangyi Zhang 002; Lei Chen 001; Chao Wang 096; Fengwei An (A-SSCC, 2021)

A Pseudo 943 million Frames Per Rate High-Speed Camera with Asynchronous Double-Frame Exposure for Motion Estimation. - Ruoheng Yao; Huanshihong Deng; Wenyue Zhang; Yangyi Zhang 002; Lei Chen 001; Fengwei An (ICTA, 2021)

Efficient VLSI Architecture for Edge Sensing Anti-Aliasing Demosaicing. - Yangyi Zhang 002; Zizhao Peng; Ruoheng Yao; Huanshihong Deng; Wenyue Zhang; Lei Chen 001; Fengwei An (ICTA, 2021)

Configurable Image Rectification and Disparity Refinement for Stereo Vision. - Pingcheng Dong; Zhuoyu Chen; Zhuoao Li; Ruoheng Yao; Wenyue Zhang; Yangyi Zhang 002; Lei Chen 001; Chao Wang 096; Fengwei An (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS. - Dongshen Zhan; Liping Zhong; Wentao Zhou; Zhenyu Yao; Xiongshi Luo; Yangyi Zhang 002; Hemiao Wang; De Zhou; Quan Pan 002 (ICTA, 2023)

A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS. - Dongfan Xu; Yangyi Zhang 002; Zhenghao Li; Xiongshi Luo; Pingyi Cai; Hongzhi Wu; Liping Zhong; Weitao Wu; Liru Zhu; Quan Pan 002 (ISCAS, 2023)

A 0.96-0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier. - Dongfan Xu; Yangyi Zhang 002; Xiongshi Luo; Zhenghao Li; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Anti-Aliasing and Anti-Color-Artifact Demosaicing for High-Resolution CMOS Image Sensor. - Yangyi Zhang 002; Xianglong Wang; Gang Shi; Zizhao Peng; Lei Chen 001; Fengwei An (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 43.3 bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale data. - Wei Zhang; Yiwei Luo; Yangyi Zhang 002; Jiaqi Ouyang; Guodong Wang; Xianglong Wang; Gang Shi; Lei Chen 001; Fengwei An (A-SSCC, 2024)

A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. - Hongzhi Wu; Weitao Wu; Liping Zhong; Xuxu Cheng; Yangyi Zhang 002; Xiongshi Luo; Dongfan Xu; Xindan Yu; Quan Pan 002 (CICC, 2024)

Live Demonstration: A Video Denoising Co-processor with Non-local Means Algorithm for FHD 30fps Image Sensor. - Ruoheng Yao; Shengming Zhou; Zhiyue Gao; Yangyi Zhang 002; Yiwei Luo; Lei Chen 001; Fengwei An (ISCAS, 2024)

7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS. - Liping Zhong; Hongzhi Wu; Yangyi Zhang 002; Xuxu Cheng; Weitao Wu; Catherine Wang; Xiongshi Luo; Taiyang Fan; Dongfan Xu; Quan Pan 002 (ISSCC, 2024)

A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. - Liping Zhong; Yangyi Zhang 002; Xiongshi Luo; Hongzhi Wu; Xuxu Cheng; Weitao Wu; Zhenghao Li; Quan Pan 002 (VLSI Technology and Circuits, 2024)

A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS. - Liping Zhong; Hongzhi Wu; Weitao Wu; Catherine Wang; Wenbo Xiao; Xiongshi Luo; Yangyi Zhang 002; Dongfan Xu; Wei Wang 433; Taiyang Fan; Zhenghao Li; Xuxu Cheng; et al. (IEEE J. Solid State Circuits, 2024)

A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS. - Hongzhi Wu; Xuxu Cheng; Liping Zhong; Yangyi Zhang 002; Weitao Wu; Xiongshi Luo; Quan Pan 002 (CICC, 2025)

36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS. - Yangyi Zhang 002; Zhenyu Yao; Wentao Zhou; Xiongshi Luo; Zhenghao Li; Dongshen Zhan; Quan Pan 002 (ISSCC, 2025)

A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS. - Liping Zhong; Hongzhi Wu; Yangyi Zhang 002; Xuxu Cheng; Weitao Wu; Catherine Wang; Xiongshi Luo; Taiyang Fan; Dongfan Xu; Zhenghao Li; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS. - Hongzhi Wu; Liping Zhong; Weitao Wu; Catherine Wang; Xuxu Cheng; Xiongshi Luo; Yangyi Zhang 002; Dongfan Xu; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

ReHIT: Reconfigurable High-Radix Iterative-Taylor Architecture for Ultraprecise Logarithm/Exponential Functions in FPGA-Based Softmax Accelerators. - Yangyi Zhang 002; Xianglong Wang; Lei Chen 001; Fengwei An (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. - Xiongshi Luo; Xuewei You; Jiahan Fu; Zhenghao Li; Liping Zhong; Mengjie Song; Taiyang Fan; Wenbo Xiao; Hongzhi Wu; Yangyi Zhang 002; Chenchang Zhan; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 100-Gb/s Burst-Mode Optical Receiver With 9-Tap Pipelined FFE and Amplitude/Phase Adaptation in 28-nm CMOS. - Pingyi Cai; Ruixian Zhang; Xiongshi Luo; Kun Zhang; Wenhan Guan; Jiayao Li; Wenkang Luo; Yangyi Zhang 002; Chenyang Wang; Quan Pan 002 (CICC, 2026)

8.9 A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces. - Xuxu Cheng; Hongzhi Wu; Zhenghao Li; Weitao Wu; Xiongshi Luo; Yangyi Zhang 002; Quan Pan 002 (ISSCC, 2026)

A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces. - Hongzhi Wu; Xuxu Cheng; Yangyi Zhang 002; Xiongshi Luo; Zhenghao Li; Weitao Wu; Quan Pan 002 (ISSCC, 2026)

A Monolithic CMOS 28Gb/s PAM-4 Optical Receiver Front-End with Lateral-Enhanced P-Well/N-Well APD for VCSEL-Based Links. - Dongshen Zhan; Hemiao Wang; Xiongshi Luo; Yangyi Zhang 002; Zhenyu Yao; Wentao Zhou; Zhenghao Li; Hongzhi Wu; De Zhou; Quan Pan 002 (OFC, 2026)

A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS. - Hongzhi Wu; Xuxu Cheng; Weitao Wu; Liping Zhong; Catherine Wang; Yangyi Zhang 002; Xiongshi Luo; Dongfan Xu; Quan Pan 002 (IEEE J. Solid State Circuits, 2026)

A 2 × 80 Gb/s Single-Ended TAS-TIS PAM-4 Receiver Front-End With Crosstalk Cancellation and Signal Reutilization in 28-nm CMOS. - Yangyi Zhang 002; Liping Zhong; Taiyang Fan; Xiongshi Luo; Hongzhi Wu; Xuxu Cheng; Weitao Wu; Wentao Zhou; Dongfan Xu; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)

A 112-Gb/s Single-Ended Receiver Front-End With Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. - Liping Zhong; Yangyi Zhang 002; Xiongshi Luo; Hongzhi Wu; Xuxu Cheng; Weitao Wu; Zhenghao Li; Quan Pan 002 (IEEE J. Solid State Circuits, 2026)