A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. - Yangzhan Mai; Mingyu Wang 003; Chuanghao Zhang; Baiqing Zhong; Zhiyi Yu (ISCAS, 2023)

A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. - Baiqing Zhong; Mingyu Wang 003; Chuanghao Zhang; Yangzhan Mai; Xiaojie Li; Zhiyi Yu (ISVLSI, 2023)

A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips. - Chuanghao Zhang; Mingyu Wang 003; Yangzhan Mai; Chengcheng Tang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. - Yicong Zhang; Mingyu Wang 003; Yangzhan Mai; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM. - Xiaojie Li; Mingyu Wang 003; Yangzhan Mai; Yicong Zhang; Baiqing Zhong; Zhiyi Yu (ISVLSI, 2024)

Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations. - Yicong Zhang; Mingyu Wang 003; Wangguang Wang; Yangzhan Mai; Haiqiu Huang; Zhiyi Yu (MICRO, 2024)