A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification. - Jinge Ma; Yanjin Lyu; Yuanqi Hu (APCCAS, 2022)

A Mismatch Compensation Scheme for Cyclic-pipelined ADC via Dynamic Element Matching Technique. - Yihao Yang; Yanjin Lyu; Yuanqi Hu (ISCAS, 2022)

A Universal Evaluation Method of Element Matching Strategies for Data Converters Based on Optimal Combination Algorithms. - Yanjin Lyu; Yuanqi Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 61 mHz - 3.4 Hz High-pass Capacitively Coupled Analog Frontend with Tunnelling Biasing and Output DC Servo Loop. - Yanjin Lyu; Jing Liang; Yuanqi Hu (ISCAS, 2023)

A Matching Strategy Based on Full-Permutation Bisection for Data Converters. - Yanjin Lyu; Yuanqi Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 2.30 NEF Split-Steering Amplifier for Switched-Capacitor Circuits With -14.2-dB CM-CM Gain and 100-V/μs Slew Rate. - Yanjin Lyu; Yuanqi Hu (IEEE J. Solid State Circuits, 2025)