Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. - Yann Civale; Deniz Sabuncuoglu Tezcan; Harold G. G. Philipsen; P. Jaenen; Rahul Agarwal; F. Duval; Philippe Soussan; Youssef Travaly; Eric Beyne (3DIC, 2009)

A novel concept for ultra-low capacitance via-last TSV. - Yann Civale; Marcel Gonzalez; Deniz Sabuncuoglu Tezcan; Youssef Travaly; Philippe Soussan; Eric Beyne (3DIC, 2010)

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. - Wei Guo; Geert Van der Plas; Andrej Ivankovic; Geert Eneman; Vladimir Cherman; Bart De Wachter; Abdelkarim Mercha; Mario Gonzalez; Yann Civale; Augusto Redolfi; Thibault Buisson; A. Jourdan; et al. (ICICDT, 2012)

Cost-effective temporary bonding and debonding material solution towards high-volume manufacturing 2.5D/3D through-silicon via integrated circuits. - Yann Civale; Herman Meynen; Ranjith S. E. John; Peng-Fei Fu; Craig R. Yeakle; Sheng Wang; Stefan Krausse; Thomas Rapps; Stefan Lutter (3DIC, 2013)