Implementation and simulation of the impact of mixer phase mismatch in cartesian feedback linearization systems. - Camilo Coelho; Yann Delomier; Dominique Dallet; Nathalie Deltimple; Eric Kerherve (ICECS, 2016)

From multicore LDPC decoder implementations to FPGA decoder architectures: a case study. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ICECS, 2018)

Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ICECS, 2018)

Model-based Design of Efficient LDPC Decoder Architectures. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ISTC, 2018)

Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (SiPS, 2019)

Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding. - Bertrand Le Gal; Yann Delomier; Camille Leroux; Christophe Jégo (SiPS, 2020)

Model-based Design of Hardware SC Polar Decoders for FPGAs. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (ACM Trans. Reconfigurable Technol. Syst., 2020)

Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices. - Yann Delomier; Bertrand Le Gal; Jérémie Crenne; Christophe Jégo (J. Signal Process. Syst., 2020)