Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. - Yannan Nellie Wu; Joel S. Emer; Vivienne Sze (ICCAD, 2019)

An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. - Yannan Nellie Wu; Vivienne Sze; Joel S. Emer (ISPASS, 2020)

Architecture-Level Energy Estimation for Heterogeneous Computing Systems. - Francis Wang; Yannan Nellie Wu; Matthew E. Woicik; Joel S. Emer; Vivienne Sze (ISPASS, 2021)

Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. - Yannan Nellie Wu; Po-An Tsai; Angshuman Parashar; Vivienne Sze; Joel S. Emer (ISPASS, 2021)

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. - Yannan Nellie Wu; Po-An Tsai; Angshuman Parashar; Vivienne Sze; Joel S. Emer (MICRO, 2022)

LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. - Michael Gilbert; Yannan Nellie Wu; Angshuman Parashar; Vivienne Sze; Joel S. Emer (ISPASS, 2023)

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. - Yannan Nellie Wu; Po-An Tsai; Saurav Muralidharan; Angshuman Parashar; Vivienne Sze; Joel S. Emer (MICRO, 2023)

Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. - Zi Yu Xue; Yannan Nellie Wu; Joel S. Emer; Vivienne Sze (MICRO, 2023)

Systematic Modeling and Design of Sparse Deep Neural Network Accelerators - Yannan Nellie Wu (2023)

LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space. - Michael Gilbert; Yannan Nellie Wu; Joel S. Emer; Vivienne Sze (CoRR, 2024)