A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2001)

A Gated Clock Scheme for Low Power Scan-Based BIST. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (IOLTW, 2001)

Test Power: a Big Issue in Large SOC Designs. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DELTA, 2002)

Power Driven Chaining of Flip-Flops in Scan Architectures. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 2002)

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (ITC, 2003)

Design of Routing-Constrained Low Power Scan Chains. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2004)

An efficient scan tree design for test time reduction. - Yannick Bonhomme; Tomokazu Yoneda; Hideo Fujiwara; Patrick Girard 001 (ETS, 2004)

Power-Driven Routing-Constrained Scan Chain Design. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2004)

Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. - Patrick Girard 001; Yannick Bonhomme (J. Low Power Electron., 2005)

A Gated Clock Scheme for Low Power Testing of Logic Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2006)

Power-On Controller for high lifetime wireless sensor nodes. - Mickael Cartron; Nathaniel Seymour; Yannick Bonhomme (WSAN, 2008)

System-level hardware-based protection of memories against soft-errors. - Valentin Gherman; Samuel Evain; Mickael Cartron; Nathaniel Seymour; Yannick Bonhomme (DATE, 2009)

Transaction-based modeling for large scale simulations of heterogeneous systems. - Richard Buchmann; Mickael Cartron; Yannick Bonhomme (SimuTools, 2009)

Programmable restricted SEC codes to mask permanent faults in semiconductor memories. - Samuel Evain; Yannick Bonhomme; Valentin Gherman (IOLTS, 2010)

Error prediction based on concurrent self-test and reduced slack time. - Valentin Gherman; J. Massas; Samuel Evain; Stéphane Chevobbe; Yannick Bonhomme (DATE, 2011)

Generalized parity-check matrices for SEC-DED codes with fixed parity. - Valentin Gherman; Samuel Evain; Nathaniel Seymour; Yannick Bonhomme (IOLTS, 2011)

Programmable extended SEC-DED codes for memory errors. - Valentin Gherman; Samuel Evain; Fabrice Auzanneau; Yannick Bonhomme (VTS, 2011)

Memory reliability improvements based on maximized error-correcting codes. - Valentin Gherman; Samuel Evain; Yannick Bonhomme (ETS, 2012)

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. - Sébastien Sarrazin; Samuel Evain; Lirida Alves de Barros Naviner; Yannick Bonhomme; Valentin Gherman (DATE, 2013)

Memory Reliability Improvement Based on Maximized Error-Correcting Codes. - Valentin Gherman; Samuel Evain; Yannick Bonhomme (J. Electron. Test., 2013)