Yannis P. Tsividis

Orcid: 0000-0002-7775-7218

According to our database1, Yannis P. Tsividis authored at least 93 papers between 1984 and 2022.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1986, "For contributions to the development of MOS analog integrated circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2019
Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time".
IEEE J. Solid State Circuits, 2018

A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption.
IEEE J. Solid State Circuits, 2018

A Case Study in Analog Co-Processing for Solving Stochastic Differential Equations.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017
Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study.
IEEE Micro, 2017

Hybrid analog-digital solution of nonlinear partial differential equations.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Design of tunable digital delay cells.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Signal processing in continuous time using asynchronous techniques.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC.
IEEE J. Solid State Circuits, 2016

Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time.
IEEE J. Solid State Circuits, 2016

Digital processing of signals produced by voltage-controlled-oscillator-based continuous-time ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design considerations for variable-rate digital signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Evaluation of an Analog Accelerator for Linear Algebra.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Derivative Level-Crossing Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 3-10fJ/conv-step 0.0032mm<sup>2</sup> error-shaping alias-free asynchronous ADC.
Proceedings of the Symposium on VLSI Circuits, 2015

Continuous-time hybrid computation with programmable nonlinearities.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate.
IEEE J. Solid State Circuits, 2014

2013
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution.
IEEE J. Solid State Circuits, 2013

A flexible, clockless digital filter.
Proceedings of the ESSCIRC 2013, 2013

2012
Internally Non-LTI Systems Based on Delays, With Application to Companding Signal Processors.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation.
IEEE J. Solid State Circuits, 2012

A Case for Hybrid Discrete-Continuous Architectures.
IEEE Comput. Archit. Lett., 2012

An event-driven, alias-free ADC with signal-dependent resolution.
Proceedings of the Symposium on VLSI Circuits, 2012

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Direct processing of mpeg audio using companding and BFP techniques.
Proceedings of the IEEE International Conference on Acoustics, 2011

2010
Externally linear time invariant digital signal processors.
IEEE Trans. Signal Process., 2010

Event-Driven Data Acquisition and Digital Signal Processing - A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Signal-Dependent Variable-Resolution Clockless A/D Conversion With Application to Continuous-Time Digital Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Event-driven, continuous-time ADCs and DSPs for adapting power dissipation to signal activity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Energy-efficient asynchronous delay element with wide controllability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Event-driven data acquisition and continuous-time digital signal processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Analysis and simulation of continuous-time digital signal processors.
Signal Process., 2009

Processing of Signals using Level-crossing Sampling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Signal-dependent Variable-resolution Quantization for Continuous-time Digital Signal Processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply.
IEEE J. Solid State Circuits, 2008

A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation.
IEEE J. Solid State Circuits, 2008

A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information.
IEEE J. Solid State Circuits, 2008

A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Correction to "A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation".
IEEE J. Solid State Circuits, 2007

A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation.
IEEE J. Solid State Circuits, 2007

Analysis of Continuous-Time Digital Signal Processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Instantaneously Companding Digital Signal Processors.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
Mixed-Domain Systems and Signal Processing Based on Input Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A VCF Loss-Control Tuning Loop for Q -Enhanced LC Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Dynamic power optimization of active filters with application to zero-IF receivers.
IEEE J. Solid State Circuits, 2006

A Continuous-Time Programmable Digital FIR Filter.
IEEE J. Solid State Circuits, 2006

A VLSI analog computer/digital computer accelerator.
IEEE J. Solid State Circuits, 2006

Ultra-Low Voltage Analog Integrated Circuits.
IEICE Trans. Electron., 2006

A Blocker-Vigilant Channel-Select Filter with Adaptive IIP3 and Power Dissipation.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Companding Digital Signal Processors.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2005
0.5-V analog circuit techniques and their application in OTA and filter design.
IEEE J. Solid State Circuits, 2005

Continuous-time DSPs, analog/digital computers and other mixed-domain circuits.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Continuous-Time Digital Signal Processors.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
A "divide and conquer" technique for implementing wide dynamic range continuous-time filters.
IEEE J. Solid State Circuits, 2004

Mixing domains in signal processing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Analysis of oscillator amplitude control, and its application to automatic tuning of quality factor for active LC filters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Digital signal processing in continuous time: a possibility for avoiding aliasing and reducing quantization error.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A 0.5-V bulk-input fully differential operational transconductance amplifier.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
Dynamic range optimization of weakly nonlinear, fully balanced, Gm-C filters with power dissipation constraints.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Micropower low-voltage analog filter in a digital CMOS process.
IEEE J. Solid State Circuits, 2003

Power-area-DR-frequency-selectivity tradeoffs in weakly nonlinear active filters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A power efficient channel selection filter/coarse AGC with no range switching transients.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers.
IEEE J. Solid State Circuits, 2002

Design techniques for automatically tuned integrated gigahertz-range active LC filters.
IEEE J. Solid State Circuits, 2002

Design considerations and experimental evaluation of a syllabic companding audio frequency filter.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Noise and power reduction in filters through the use of adjustable biasing.
IEEE J. Solid State Circuits, 2001

Continuous-time filters in telecommunications chips.
IEEE Commun. Mag., 2001

Generalized chopper stabilization.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

"Noninvasive" techniques for syllabic companding in signal processors.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A "divide and conquer" technique for the design of wide dynamic range continuous time filters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An anti-blocker structure MOSFET-C filter for a direct conversion receiver.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Widely programmable high-frequency continuous-time filters in digital CMOS technology.
IEEE J. Solid State Circuits, 2000

1999
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Signal analysis of externally linear filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Mixed analog-digital fuzzy logic controller with continuous-amplitude fuzzy inferences and defuzzification.
IEEE Trans. Fuzzy Syst., 1998

1997
Six-terminal MOSFET's: modeling and applications in highly linear, electronically tunable resistors.
IEEE J. Solid State Circuits, 1997

1996
A Si 1.8 GHz RLC filter with tunable center frequency and quality factor.
IEEE J. Solid State Circuits, 1996

Design and implementation of a CMOS operational amplifier architecture with dual common-mode feedback loop.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Design considerations and implementation of very low frequency continuous-time CMOS monolithic filters.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994
MOSFET modeling for analog circuit CAD: problems and prospects.
IEEE J. Solid State Circuits, March, 1994

Integrated continuous-time filter design - an overview.
IEEE J. Solid State Circuits, March, 1994

Design of Active RLC Integrated Filters with Application in the GHz Range.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Design Considerations for Highly Linear Electronically Tunable Resistor.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Bounds on Noise in Integrated Active-RC and MOSFET-C Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Comparative Study of Five Integrator Structures for Monolithic Continuous-time Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1989
A Reconfigurable Analog VLSI Neural Network Chip.
Proceedings of the Advances in Neural Information Processing Systems 2, 1989

1988
Analog MOS circuit techniques in the VLSI implementation of neural networks.
Neural Networks, 1988

1985
Time- and Frequency-Domain Analysis of Linear Switched-Capacitor Networks Using State Charge Variables.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

1984
Problems in Precision Modeling of the MOS Transistor for Analog Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984


  Loading...