System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms. - Benton H. Calhoun; Sudhanshu Khanna; Yanqing Zhang 002; Joseph F. Ryan 002; Brian P. Otis (ISCAS, 2010)

A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS. - Yousef Shakhsheer; Yanqing Zhang 002; Brian P. Otis; Benton H. Calhoun (CICC, 2012)

A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC. - Fan Zhang 049; Yanqing Zhang 002; Jason Silver; Yousef Shakhsheer; Manohar Nagaraju; Alicia Klinefelter; Jagdish Nayayan Pandey; James Boley; Eric J. Carlson; Aatmesh Shrivastava; Brian P. Otis; Benton H. Calhoun (ISSCC, 2012)

Body Sensor Networks: A Holistic Approach From Silicon to Users. - Benton H. Calhoun; John C. Lach; John A. Stankovic; David D. Wentzloff; Kamin Whitehouse; Adam T. Barth; Jonathan K. Brown; Qiang Li 025; Seunghyun Oh; Nathan E. Roberts; Yanqing Zhang 002 (Proc. IEEE, 2012)

A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC. - Alicia Klinefelter; Yanqing Zhang 002; Brian P. Otis; Benton H. Calhoun (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications. - Yanqing Zhang 002; Fan Zhang 049; Yousef Shakhsheer; Jason Silver; Alicia Klinefelter; Manohar Nagaraju; James Boley; Jagdish Nayayan Pandey; Aatmesh Shrivastava; Eric J. Carlson; Austin Wood; Benton H. Calhoun; et al. (IEEE J. Solid State Circuits, 2013)

Fast, accurate variation-aware path timing computation for sub-threshold circuits. - Yanqing Zhang 002; Benton H. Calhoun (ISQED, 2014)

21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios. - Alicia Klinefelter; Nathan E. Roberts; Yousef Shakhsheer; Patricia González; Aatmesh Shrivastava; Abhishek Roy 002; Kyle Craig; Muhammad Faisal; James Boley; Seunghyun Oh; Yanqing Zhang 002; Divya Akella; et al. (ISSCC, 2015)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

PRIMAL: Power Inference using Machine Learning. - Yuan Zhou; Haoxing Ren; Yanqing Zhang 002; Ben Keller; Brucek Khailany; Zhiru Zhang (DAC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. - Zhiyao Xie; Guan-Qi Fang; Yu-Hung Huang; Haoxing Ren; Yanqing Zhang 002; Brucek Khailany; Shao-Yun Fang; Jiang Hu; Yiran Chen 001; Erick Carvajal Barboza (ASP-DAC, 2020)

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. - Yanqing Zhang 002; Haoxing Ren; Brucek Khailany (DAC, 2020)

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk). - Yanqing Zhang 002; Haoxing Ren; Brucek Khailany (ICCAD, 2020)

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk). - Yanqing Zhang 002; Haoxing Ren; Ben Keller; Brucek Khailany (ICCAD, 2020)

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. - Vidya A. Chhabria; Yanqing Zhang 002; Haoxing Ren; Ben Keller; Brucek Khailany; Sachin S. Sapatnekar (CoRR, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Accelerating Chip Design With Machine Learning. - Brucek Khailany; Haoxing Ren; Steve Dai; Saad Godil; Ben Keller; Robert Kirby 001; Alicia Klinefelter; Rangharajan Venkatesan; Yanqing Zhang 002; Bryan Catanzaro; William J. Dally (IEEE Micro, 2020)

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. - Vidya A. Chhabria; Yanqing Zhang 002; Haoxing Ren; Ben Keller; Brucek Khailany; Sachin S. Sapatnekar (DATE, 2021)

2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting. - Ghasem Pasandi; Sreedhar Pratty; David Brown; Yanqing Zhang 002; Haoxing Ren; Brucek Khailany (ICCAD, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

GATSPI: GPU accelerated gate-level simulation for power improvement. - Yanqing Zhang 002; Haoxing Ren; Akshay Sridharan; Brucek Khailany (DAC, 2022)

Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper). - Haoxing Ren; Siddhartha Nath; Yanqing Zhang 002; Hao Chen 059; Mingjie Liu (ICCAD, 2022)

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus. - Dian-Lun Lin; Haoxing Ren; Yanqing Zhang 002; Brucek Khailany; Tsung-Wei Huang (ICPP, 2022)

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning. - Vidya A. Chhabria; Ben Keller; Yanqing Zhang 002; Sandeep Vollala; Sreedhar Pratty; Haoxing Ren; Brucek Khailany (MLCAD, 2022)

GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs. - Dian-Lun Lin; Yanqing Zhang 002; Haoxing Ren; Brucek Khailany; Shih-Hsin Wang; Tsung-Wei Huang (DAC, 2023)

Machine Learning and Algorithms: Let Us Team Up for EDA. - Haoxing Ren; Brucek Khailany; Matthew Fojtik; Yanqing Zhang 002 (IEEE Des. Test, 2023)

BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation. - Yingjie Li; Anthony Agnesina; Yanqing Zhang 002; Haoxing Ren; Cunxi Yu (DATE, 2024)

GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method. - Yanqing Zhang 002; Haoxing Ren; Brucek Khailany (ICCAD, 2024)

ChipVQA: Benchmarking Visual Language Models for Chip Design. - Haoyu Yang; Qijing Huang 001; Nathaniel Ross Pinckney; Walker J. Turner; Wenfei Zhou; Yanqing Zhang 002; Chia-Tung Ho; Chen-Chia Chang; Haoxing Ren (DATE, 2025)

SimPart: A Simple Yet Effective Replication-Aided Partitioning Algorithm for Logic Simulation on GPU. - Yi-Hua Chung; Shui Jiang; Wan-Luan Lee; Yanqing Zhang 002; Haoxing Ren; Tsung-Yi Ho; Tsung-Wei Huang (Euro-Par (3), 2025)