A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. - Ching-Lung Su; Wei-Sen Yang; Ya-Li Chen; Yao-Chang Yang; Ching-Wen Chen; Jiun-In Guo; Shau-Yin Tseng (APCCAS, 2006)

A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. - Yao-Chang Yang; Chien-Chang Lin; Hsui-Cheng Chang; Ching-Lung Su; Jiun-In Guo (ICME, 2006)

A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. - Hsiu-Cheng Chang; Jia-Wei Chen; Ching-Lung Su; Yao-Chang Yang; Yao Li; Chun-Hao Chang; Ze-Min Chen; Wei-Sen Yang; Chien-Chang Lin; Ching-Wen Chen; Jinn-Shyan Wang; Jiun-In Guo (ISSCC, 2007)

A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. - Chun-Hao Chang; Jia-Wei Chen; Hsiu-Cheng Chang; Yao-Chang Yang; Jinn-Shyan Wang; Jiun-In Guo (SiPS, 2007)

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. - Chien-Chang Lin; Jia-Wei Chen; Hsiu-Cheng Chang; Yao-Chang Yang; Yi-Huan Ou-Yang; Ming-Chih Tsai; Jiun-In Guo; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2007)

A dynamic quality-scalable H.264 video encoder chip. - Hsiu-Cheng Chang; Yao-Chang Yang; Jia-Wei Chen; Ching-Lung Su; Cheng-An Chien; Jiun-In Guo; Jinn-Shyan Wang (ASP-DAC, 2009)

A Dynamic Quality-scalable H.264 Video Encoder. - Hsiu-Cheng Chang; Jia-Wei Chen; Yao-Chang Yang; Cheng-An Chien; Tzu-Chun Chang; Jinn-Shyan Wang; Jiun-In Guo (ISCAS, 2009)

High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV Applications. - Yao-Chang Yang; Jiun-In Guo (IEEE Trans. Circuits Syst. Video Technol., 2009)

Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC. - Chih-Chuan Yang; Kheng-Joo Tan; Yao-Chang Yang; Jiun-In Guo (ICME, 2010)

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. - Cheng-An Chien; Yao-Chang Yang; Hsiu-Cheng Chang; Jia-Wei Chen; Cheng-Yen Chang; Jiun-In Guo; Jinn-Shyan Wang; Ching-Hwa Cheng (ASP-DAC, 2011)