Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. - Swathi T. Gurumani; Jacob Tolar; Yao Chen 008; Yun Liang 001; Kyle Rupnow; Deming Chen (FCCM, 2014)

System-level design solutions: Enabling the IoT explosion. - Liwei Yang; Yao Chen 008; Wei Zuo; Tan Nguyen; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (ASICON, 2015)

High Level Synthesis of Complex Applications: An H.264 Video Decoder. - Xinheng Liu; Yao Chen 008; Tan Nguyen; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (FPGA, 2016)

SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. - Tan Nguyen; Yao Chen 008; Kyle Rupnow; Swathi T. Gurumani; Deming Chen (ISVLSI, 2016)

FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. - Ying Chen; Tan Nguyen; Yao Chen 008; Swathi T. Gurumani; Yun Liang 001; Kyle Rupnow; Jason Cong; Wen-mei W. Hwu; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. - Yao Chen 008; Swathi T. Gurumani; Yun Liang 001; Guofeng Li; Donghui Guo; Kyle Rupnow; Deming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2016)

HASS: High Accuracy Spike Sorting with Wavelet Package Decomposition and Mutual Information. - Yao Chen 008; Libo Huang; Jiong He; Kunyao Zhao; Ruichu Cai; Zhifeng Hao (BIBM, 2018)

HaaS: Cloud-Based Real-Time Data Analytics with Heterogeneity-Aware Scheduling. - Jiong He; Yao Chen 008; Tom Z. J. Fu; Xin Long; Marianne Winslett; Liang You; Zhenjie Zhang (ICDCS, 2018)

A locality-aware shuffle optimization on fat-tree data centers. - Jihe Wang; Danghui Wang; Meikang Qiu; Yao Chen 008; Bing Guo (Future Gener. Comput. Syst., 2018)

Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs. - Yao Chen 008; Jiong He; Xiaofan Zhang 001; Cong Hao; Deming Chen (FPGA, 2019)

On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs. - Xinyu Chen 001; Ronak Bajaj; Yao Chen 008; Jiong He; Bingsheng He; Weng-Fai Wong; Deming Chen (FPL, 2019)

NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. - Cong Hao; Yao Chen 008; Xinheng Liu; Atif Sarwari; Daryl Sew; Ashutosh Dhar; Bryan Wu; Dongdong Fu; Jinjun Xiong; Wen-Mei Hwu; Junli Gu; Deming Chen (ICCAD, 2019)

µL2Q: An Ultra-Low Loss Quantization Method for DNN Compression. - Cheng Gong; Tao Li 022; Ye Lu 004; Cong Hao; Xiaofan Zhang 001; Deming Chen; Yao Chen 008 (IJCNN, 2019)

Pico-Ampere Voltage References for IoT Systems. - Huachao Xu; Jinlong Hu; Yao Chen 008; Guofeng Li; Chao Lu 005 (ISCAS, 2019)

T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA. - Yao Chen 008; Kai Zhang; Cheng Gong; Cong Hao; Xiaofan Zhang 001; Tao Li 022; Deming Chen (ISVLSI, 2019)

A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices. - Xiaofan Zhang 001; Cong Hao; Yuhong Li; Yao Chen 008; Jinjun Xiong; Wen-Mei W. Hwu; Deming Chen (CoRR, 2019)

TAG : Type Auxiliary Guiding for Code Comment Generation. - Ruichu Cai; Zhihao Liang; Boyan Xu; Zijian Li 001; Yuexing Hao; Yao Chen 008 (ACL, 2020)

Is FPGA Useful for Hash Joins? - Xinyu Chen 001; Yao Chen 008; Ronak Bajaj; Jiong He; Bingsheng He; Weng-Fai Wong; Deming Chen (CIDR, 2020)

EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. - Yuhong Li; Cong Hao; Xiaofan Zhang 001; Xinheng Liu; Yao Chen 008; Jinjun Xiong; Wen-mei W. Hwu; Deming Chen (DAC, 2020)

Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. - Cong Hao; Yao Chen 008; Xiaofan Zhang 001; Yuhong Li; Jinjun Xiong; Wen-Mei Hwu; Deming Chen (ACM Great Lakes Symposium on VLSI, 2020)

HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy. - Yao Chen 008; Xin Long; Jiong He; Yuhang Chen; Hongshi Tan; Zhenxiang Zhang; Marianne Winslett; Deming Chen (ICDCS, 2020)

WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. - Xinheng Liu; Yao Chen 008; Cong Hao; Ashutosh Dhar; Deming Chen (ASAP, 2021)

MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. - Lixiang Li 003; Yao Chen 008; Zacharie Zirnheld; Pan Li 005; Cong Hao (DAC, 2021)

Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS. - Xinyu Chen 001; Hongshi Tan; Yao Chen 008; Bingsheng He; Weng-Fai Wong; Deming Chen (DAC, 2021)

ThunderGP: HLS-based Graph Processing Framework on FPGAs. - Xinyu Chen 001; Hongshi Tan; Yao Chen 008; Bingsheng He; Weng-Fai Wong; Deming Chen (FPGA, 2021)

3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency Acceleration. - Yao Chen 008; Cole Hawkins; Kaiqi Zhang 002; Zheng Zhang 005; Cong Hao (ACM Great Lakes Symposium on VLSI, 2021)

ThundeRiNG: generating multiple independent random number sequences on FPGAs. - Hongshi Tan; Xinyu Chen 001; Yao Chen 008; Bingsheng He; Weng-Fai Wong (ICS, 2021)

3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low BitwidthQuantization, and Ultra-Low Latency Acceleration. - Yao Chen 008; Cole Hawkins; Kaiqi Zhang 002; Zheng Zhang 005; Cong Hao (CoRR, 2021)

Free Lunch for Co-Saliency Detection: Context Adjustment. - Lingdong Kong; Prakhar Ganesh; Tan Wang; Junhao Liu 001; Yao Chen 008; Le Zhang (CoRR, 2021)

Compressing Large-Scale Transformer-Based Models: A Case Study on BERT. - Prakhar Ganesh; Yao Chen 008; Xin Lou; Mohammad Ali Khan; Yin Yang 001; Hassan Sajjad 001; Preslav Nakov; Deming Chen; Marianne Winslett (Trans. Assoc. Comput. Linguistics, 2021)

VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. - Cheng Gong; Yao Chen 008; Ye Lu 004; Tao Li 022; Cong Hao; Deming Chen (IEEE Trans. Computers, 2021)

Learning-Based Simultaneous Detection and Characterization of Time Delay Attack in Cyber-Physical Systems. - Prakhar Ganesh; Xin Lou; Yao Chen 008; Rui Tan 001; David K. Y. Yau; Deming Chen; Marianne Winslett (IEEE Trans. Smart Grid, 2021)

HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation. - Xinheng Liu; Yao Chen 008; Prakhar Ganesh; Junhao Pan; Jinjun Xiong; Deming Chen (ASP-DAC, 2022)

ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines. - Xinyu Chen 001; Yao Chen 008; Feng Cheng; Hongshi Tan; Bingsheng He; Weng-Fai Wong (MICRO, 2022)

YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs. - Prakhar Ganesh; Yao Chen 008; Yin Yang 001; Deming Chen; Marianne Winslett (WACV, 2022)

Efficient Machine Learning, Compilers, and Optimizations for Embedded Systems. - Xiaofan Zhang 001; Yao Chen 008; Cong Hao; Sitao Huang; Yuhong Li; Deming Chen (CoRR, 2022)

HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation. - Yao Chen 008; Junhao Pan; Xinheng Liu; Jinjun Xiong; Deming Chen (CoRR, 2022)

ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS. - Xinyu Chen 001; Feng Cheng; Hongshi Tan; Yao Chen 008; Bingsheng He; Weng-Fai Wong; Deming Chen (ACM Trans. Reconfigurable Technol. Syst., 2022)

HongTu: Scalable Full-Graph GNN Training on Multiple GPUs (via communication-optimized CPU data offloading). - Qiange Wang; Yao Chen 008; Weng-Fai Wong; Bingsheng He (CoRR, 2023)

Cybersecurity for Modern Smart Grid Against Emerging Threats. - Daisuke Mashima; Yao Chen 008; Muhammad M. Roomi; Subhash Lakshminarayana; Deming Chen (Found. Trends Priv. Secur., 2023)

LightRW: FPGA Accelerated Graph Dynamic Random Walks. - Hongshi Tan; Xinyu Chen 001; Yao Chen 008; Bingsheng He; Weng-Fai Wong (Proc. ACM Manag. Data, 2023)

NIOT: A Novel Inference Optimization of Transformers on Modern CPUs. - Zining Zhang 001; Yao Chen 008; Bingsheng He; Zhenjie Zhang (IEEE Trans. Parallel Distributed Syst., 2023)

HongTu: Scalable Full-Graph GNN Training on Multiple GPUs. - Qiange Wang; Yao Chen 008; Weng-Fai Wong; Bingsheng He (Proc. ACM Manag. Data, 2023)

T-Edge: Trusted Heterogeneous Edge Computing. - Jiamin Shen; Yao Chen 008; Weng-Fai Wong; Ee-Chien Chang (ACSAC, 2024)

Deep Feature Surgery: Towards Accurate and Efficient Multi-exit Networks. - Cheng Gong; Yao Chen 008; Qiuyang Luo; Ye Lu 004; Tao Li 022; Yuzhi Zhang; Yufei Sun; Le Zhang (ECCV (49), 2024)

Aggressive Post-Training Compression on Extremely Large Language Models. - Zining Zhang 001; Yao Chen 008; Bingsheng He; Zhenjie Zhang (CoRR, 2024)

Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs. - Kunpeng Xie; Ye Lu 004; Xinyu He 002; Dezhi Yi; Huijuan Dong; Yao Chen 008 (ACM Trans. Archit. Code Optim., 2024)

Introduction to the Special Issue on FPGA-based Embedded Systems for Industrial and IoT Applications. - Satwant Singh; Carlos Enrique Montenegro-Marín; Yun (Eric) Liang; Yao Chen 008; Nele Mentens; Raymond Nijssen (ACM Trans. Reconfigurable Technol. Syst., 2024)

Vista: Vector Indexing and Search for Large-Scale Imbalanced Datasets. - Yujian Fu; Cheng Chen 008; Yao Chen 008; Weng-Fai Wong; Bingsheng He (ICDE, 2025)

ScalaGBM: Memory Efficient GBDT Training for High-Dimensional Data on GPU. - Borui Xu; Zeyi Wen; Yao Chen 008; Weiguo Liu; Weng-Fai Wong; Bingsheng He (KDD (1), 2025)

Evaluating Small Language Models for News Summarization: Implications and Factors Influencing Performance. - Borui Xu; Yao Chen 008; Zeyi Wen; Weiguo Liu; Bingsheng He (NAACL (Long Papers), 2025)

Revisiting the Design of In-Memory Dynamic Graph Storage. - Jixian Su; Chiyu Hao; Shixuan Sun; Hao Zhang 098; Sen Gao; Jiaxin Jiang; Yao Chen 008; Chenyi Zhang 002; Bingsheng He; Minyi Guo (Proc. ACM Manag. Data, 2025)

Clementi: Efficient Load Balancing and Communication Overlap for Multi-FPGA Graph Processing. - Feng Yu 003; Hongshi Tan; Xinyu Chen 001; Yao Chen 008; Bingsheng He; Weng-Fai Wong (Proc. ACM Manag. Data, 2025)

HLStrans: Dataset for LLM-Driven C-to-HLS Hardware Code Synthesis. - Qingyun Zou; Nuo Chen 002; Yao Chen 008; Bingsheng He; Weng-Fai Wong (CoRR, 2025)

Scalable and Load-Balanced Full-Graph GNN Training on Multiple GPUs. - Qiange Wang; Yao Chen 008; Weng-Fai Wong; Bingsheng He (IEEE Trans. Knowl. Data Eng., 2025)