A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. - Ming-Pin Chen; Lai-Fu Chen; Meng-Fan Chang; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Mon-Shu Ho; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (VLSIC, 2012)

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. - Meng-Fan Chang; Ming-Bin Chen; Lai-Fu Chen; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. - Chun-Hsiung Hung; Meng-Fan Chang; Yih-Shan Yang; Yao-Jen Kuo; Tzu-Neng Lai; Shin-Jang Shen; Jo-Yu Hsu; Shuo-Nan Hung; Hang-Ting Lue; Yen-Hao Shih; Shih-Lin Huang; Ti-Wen Chen; et al. (IEEE J. Solid State Circuits, 2015)