Digital assisted high-order multi-bit analog to digital ramp converters. - Yao Liu 013; Edoardo Bonizzoni; Franco Maloberti (ECCTD, 2011)

A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply. - Yao Liu 013; Edoardo Bonizzoni; Alessandro D'Amato; Franco Maloberti (ESSCIRC, 2013)

High-order multi-bit incremental converter with Smart-DEM algorithm. - Yao Liu 013; Edoardo Bonizzoni; Franco Maloberti (ISCAS, 2013)

A 2+1 multi-bit incremental architecture using Smart-DEM algorithm. - Yao Liu 013; Edoardo Bonizzoni; Franco Maloberti (ISCAS, 2014)

A single Op-Amp 0+2 sigma-delta modulator. - Yao Liu 013; Edoardo Bonizzoni; Franco Maloberti (ISCAS, 2015)

Design Strategies for High-resolution High-speed Flash-assisted Pipelined SAR ADCs. - Mustafa Oz; Edoardo Bonizzoni; Franco Maloberti; Alper Akdikmen; Yao Liu 013 (ICECS 2022, 2022)

Linearity Analysis of BiCMOS Coherent TIAs. - Xiaowei Liu; Edoardo Bonizzoni; Yao Liu 013; Franco Maloberti (PRIME, 2022)

Design of Phase-Interpolator Based Open-Loop Fractional Output Dividers. - Xiaowei Liu; Edoardo Bonizzoni; Franco Maloberti; Alper Akdikmen; Haibin Liu; Yao Liu 013 (ICECS, 2023)