A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. - Yu-Zhe Wang; Yao-Pin Wang; Yi-Chung Wu; Chia-Hsiang Yang (VLSI Circuits, 2018)

A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals. - Yu-Zhe Wang; Yao-Pin Wang; Yi-Chung Wu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2019)

Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax. - Yao-Pin Wang; Chi-Chih Wen; Chen-Chien Kao; Chung-Jung Huang; Der-Zheng Liu; Chia-Hsiang Yang (GLOBECOM, 2020)

Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. - Herming Chiueh; Chia-Hsiang Yang; Charles H.-P. Wen; Chao-Guang Yang; Po-Hao Chien; Ching-Yang Hung; Yu-Jui Chen; Yao-Pin Wang; Chin-Fong Chiu; Jer Lin (VLSI-DAT, 2020)