A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. - Yao-Sheng Hu; Chi-Huai Shih; Hung-Yen Tai; Hung-Wei Chen; Hsin-Shu Chen (A-SSCC, 2014)

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. - Hung-Yen Tai; Yao-Sheng Hu; Hung-Wei Chen; Hsin-Shu Chen (ISSCC, 2014)

A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC. - Yao-Sheng Hu; Po-Chao Huang; Mi-Ti Yang; Shih-Wei Wu; Hsin-Shu Chen (A-SSCC, 2016)

A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique. - Yao-Sheng Hu; Kai-Yue Lin; Hsin-Shu Chen (A-SSCC, 2016)

An 8-bit 900MS/S two-step SAR ADC. - Po-Chao Huang; Yao-Sheng Hu; Hung-Yen Tai; Hsin-Shu Chen (ISCAS, 2016)

A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. - Yao-Sheng Hu; Po-Chao Huang; Hung-Yen Tai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. - Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen (A-SSCC, 2018)

An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. - Yao-Sheng Hu; Jhao-Huei Lin; Ding-Guo Lin; Kai-Yue Lin; Hsin-Shu Chen (A-SSCC, 2018)

A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. - Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen (IEEE J. Solid State Circuits, 2019)