Efficient Timing Channel Protection for On-Chip Networks. - Yao Wang 008; G. Edward Suh (NOCS, 2012)

Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication. - Nithin Michael; Yao Wang 008; G. Edward Suh; Ao Tang (NOCS, 2013)

Timing channel protection for a shared memory controller. - Yao Wang 008; Andrew Ferraiuolo; G. Edward Suh (HPCA, 2014)

A Hardware Design Language for Timing-Sensitive Information-Flow Security. - Danfeng Zhang; Yao Wang 008; G. Edward Suh; Andrew C. Myers (ASPLOS, 2015)

SecDCP: secure dynamic cache partitioning for efficient timing channel protection. - Yao Wang 008; Andrew Ferraiuolo; Danfeng Zhang; Andrew C. Myers; G. Edward Suh (DAC, 2016)

Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller. - Andrew Ferraiuolo; Yao Wang 008; Danfeng Zhang; Andrew C. Myers; G. Edward Suh (HPCA, 2016)

Secure Dynamic Memory Scheduling Against Timing Channel Attacks. - Yao Wang 008; Benjamin Wu; G. Edward Suh (HPCA, 2017)