Switch module design with application to two-dimensional segmentation design. - Kai Zhu 001; D. F. Wong 001; Yao-Wen Chang (ICCAD, 1993)

A new global routing algorithm for FPGAs. - Yao-Wen Chang; Shashidhar Thakur; Kai Zhu 001; D. F. Wong 001 (ICCAD, 1994)

FPGA global routing based on a new congestion metric. - Yao-Wen Chang; D. F. Wong 001; C. K. Wong (ICCD, 1995)

Design and analysis of FPGA/FPIC switch modules. - Yao-Wen Chang; D. F. Wong 001; C. K. Wong (ICCD, 1995)

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. - Chung-Ping Chen; Yao-Wen Chang; D. F. Wong 001 (DAC, 1996)

Universal Switch-Module Design for Symmetric-Array-Based FPGAs. - Yao-Wen Chang; D. F. Wong 001; C. K. Wong (FPGA, 1996)

Universal switch modules for FPGA design. - Yao-Wen Chang; D. F. Wong 001; C. K. Wong (ACM Trans. Design Autom. Electr. Syst., 1996)

Algorithms for an FPGA switch module routing problem with application to global routing. - Shashidhar Thakur; Yao-Wen Chang; Martin D. F. Wong; S. Muthukrishnan 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Graph matching-based algorithms for FPGA segmentation design. - Yao-Wen Chang; Jai-Ming Lin; D. F. Wong 001 (ICCAD, 1998)

Switch-matrix architecture and routing for FPDs. - Guang-Ming Wu; Yao-Wen Chang (ISPD, 1998)

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. - Iris Hui-Ru Jiang; Jing-Yang Jou; Yao-Wen Chang (DAC, 1999)

Universal Switch Blocks for Three-Dimensional FPGA Design. - Guang-Ming Wu; Michael Shyu; Yao-Wen Chang (FPGA, 1999)

A clustering- and probability-based approach for time-multiplexed FPGA partitioning. - Mango Chia-Tso Chao; Guang-Ming Wu; Iris Hui-Ru Jiang; Yao-Wen Chang (ICCAD, 1999)

Quasi-Universal Switch Matrices for FPD Design. - Guang-Ming Wu; Yao-Wen Chang (IEEE Trans. Computers, 1999)

An architecture-driven metric for simultaneous placement and global routing for FPGAs. - Yao-Wen Chang; Yu-Tsang Chang (DAC, 2000)

B*-Trees: a new representation for non-slicing floorplans. - Yun-Chih Chang; Yao-Wen Chang; Guang-Ming Wu; Shu-Wei Wu (DAC, 2000)

Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. - Song-Ra Pan; Yao-Wen Chang (ICCD, 2000)

Rectilinear Block Placement Using B*-Trees. - Guang-Ming Wu; Yun-Chih Chang; Yao-Wen Chang (ICCD, 2000)

Optimal reliable crosstalk-driven interconnect optimization. - Iris Hui-Ru Jiang; Song-Ra Pan; Yao-Wen Chang; Jing-Yang Jou (ISPD, 2000)

Generic Universal Switch Blocks. - Michael Shyu; Guang-Ming Wu; Yu-Dong Chang; Yao-Wen Chang (IEEE Trans. Computers, 2000)

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Timing-driven routing for symmetrical array-based FPGAs. - Yao-Wen Chang; Kai Zhu 001; D. F. Wong 001 (ACM Trans. Design Autom. Electr. Syst., 2000)

TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. - Jai-Ming Lin; Yao-Wen Chang (DAC, 2001)

Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. - Tai-Chen Chen; Song-Ra Pan; Yao-Wen Chang (ICCD, 2001)

An Algorithm for Dynamically Reconfigurable FPGA Placement. - Guang-Ming Wu; Jai-Ming Lin; Yao-Wen Chang (ICCD, 2001)

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. - Guang-Ming Wu; Jai-Ming Lin; Mango Chia-Tso Chao; Yao-Wen Chang (ICCD, 2001)

Matching-based algorithm for FPGA channel segmentation design. - Yao-Wen Chang; Jai-Ming Lin; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Generic ILP-based approaches for time-multiplexed FPGA partitioning. - Guang-Ming Wu; Jai-Ming Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. - Jai-Ming Lin; Hsin-Lung Chen; Yao-Wen Chang (DATE, 2002)

A novel framework for multilevel routing considering routability and performance. - Shih-Ping Lin 001; Yao-Wen Chang (ICCAD, 2002)

Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. - Nicholas Chia-Yuan Chang; Yao-Wen Chang; Iris Hui-Ru Jiang (ISQED, 2002)

Comment on Generic Universal Switch Blocks. - Hongbing Fan; Yu-Liang Wu; Yao-Wen Chang (IEEE Trans. Computers, 2002)

Performance-driven placement for dynamically reconfigurable FPGAs. - Guang-Ming Wu; Jai-Ming Lin; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2002)

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. - Jai-Ming Lin; Hsin-Lung Chen; Yao-Wen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. - Yu-Min Lee; Charlie Chung-Ping Chen; Yao-Wen Chang; Martin D. F. Wong (VLSI Design, 2002)

Simultaneous floorplanning and buffer block planning. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (ASP-DAC, 2003)

Noise-aware buffer planning for interconnect-driven floorplanning. - Katherine Shu-Min Li; Yih-Huai Cherng; Yao-Wen Chang (ASP-DAC, 2003)

Graph matching-based algorithms for array-based FPGA segmentation design and routing. - Jai-Ming Lin; Song-Ra Pan; Yao-Wen Chang (ASP-DAC, 2003)

Multilevel floorplanning/placement for large-scale modules using B*-trees. - Hsun-Cheng Lee; Yao-Wen Chang; Jer-Ming Hsu; Hannah Honghua Yang (DAC, 2003)

A Fast Crosstalk- and Performance-Driven Multilevel Routing System. - Tsung-Yi Ho; Yao-Wen Chang; Sao-Jie Chen; D. T. Lee (ICCAD, 2003)

Analysis of FPGA/FPIC switch modules. - Yao-Wen Chang; Kai Zhu 001; Guang-Ming Wu; D. F. Wong 001; C. K. Wong (ACM Trans. Design Autom. Electr. Syst., 2003)

Rectilinear block placement using B*-trees. - Guang-Ming Wu; Yun-Chih Chang; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2003)

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. - Jai-Ming Lin; Yao-Wen Chang; Shih-Ping Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. - Yi-Hui Cheng; Yao-Wen Chang (ASP-DAC, 2004)

Layout techniques for on-chip interconnect inductance reduction. - Shang-Wei Tu; Jing-Yang Jou; Yao-Wen Chang (ASP-DAC, 2004)

Temporal floorplanning using 3D-subTCG. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang; Hsin-Lung Chen (ASP-DAC, 2004)

Efficient power/ground network analysis for power integrity-driven design methodology. - Su-Wei Wu; Yao-Wen Chang (DAC, 2004)

Temporal floorplanning using the T-tree formulation. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ICCAD, 2004)

Placement with Alignment and Performance Constraints Using the B*-Tree Representation. - Meng-Chen Wu; Yao-Wen Chang (ICCD, 2004)

RLC effects on worst-case switching pattern for on-chip buses. - Shang-Wei Tu; Jing-Yang Jou; Yao-Wen Chang (ISCAS (2), 2004)

Multilevel routing with antenna avoidance. - Tsung-Yi Ho; Yao-Wen Chang; Sao-Jie Chen (ISPD, 2004)

A clustering- and probability-based approach for time-multiplexed FPGA partitioning. - Guang-Ming Wu; Mango Chia-Tso Chao; Yao-Wen Chang (Integr., 2004)

MR: a new framework for multilevel full-chip routing. - Yao-Wen Chang; Shih-Ping Lin 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Simultaneous floor plan and buffer-block optimization. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. - Jai-Ming Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Timing modeling and optimization under the transmission line model. - Tai-Chen Chen; Song-Ra Pan; Yao-Wen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Multilevel full-chip gridless routing considering optical proximity correction. - Tai-Chen Chen; Yao-Wen Chang (ASP-DAC, 2005)

Placement with symmetry constraints for analog layout design using TCG-S. - Jai-Ming Lin; Guang-Ming Wu; Yao-Wen Chang; Jen-Hui Chuang (ASP-DAC, 2005)

SoC test scheduling using the B-tree based floorplanning technique. - Jen-Yi Wuu; Tung-Chieh Chen; Yao-Wen Chang (ASP-DAC, 2005)

Multilevel full-chip routing for the X-based architecture. - Tsung-Yi Ho; Chen-Feng Chang; Yao-Wen Chang; Sao-Jie Chen (DAC, 2005)

An exact jumper insertion algorithm for antenna effect avoidance/fixing. - Bor-Yiing Su; Yao-Wen Chang (DAC, 2005)

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. - Tung-Chieh Chen; Yao-Wen Chang; Shyh-Chang Lin (ICCAD, 2005)

A routing algorithm for flip-chip design. - Jia-Wei Fang; I-Jye Lin; Ping-Hung Yuh; Yao-Wen Chang; Jyh-Herng Wang (ICCAD, 2005)

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. - Shang-Wei Tu; Jing-Yang Jou; Yao-Wen Chang (ISCAS (4), 2005)

Joint exploration of architectural and physical design spaces with thermal consideration. - Yen-Wei Wu; Chia-Lin Yang; Ping-Hung Yuh; Yao-Wen Chang (ISLPED, 2005)

Modern floorplanning based on fast simulated annealing. - Tung-Chieh Chen; Yao-Wen Chang (ISPD, 2005)

NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. - Tung-Chieh Chen; Tien-Chang Hsu; Zhe-Wei Jiang; Yao-Wen Chang (ISPD, 2005)

Reconfigurable Platform for Content Science Research. - Chi-Sheng Shih 001; Chia-Lin Yang; Mong-Kai Ku; Tei-Wei Kuo; Shao-Yi Chien; Yao-Wen Chang; Liang-Gee Chen (RTCSA, 2005)

Crosstalk- and performance-driven multilevel full-chip routing. - Tsung-Yi Ho; Yao-Wen Chang; Sao-Jie Chen; D. T. Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

TCG: A transitive closure graph-based representation for general floorplans. - Jai-Ming Lin; Yao-Wen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A novel framework for multilevel full-chip gridless routing. - Tai-Chen Chen; Yao-Wen Chang; Shyh-Chang Lin (ASP-DAC, 2006)

Simultaneous block and I/O buffer floorplanning for flip-chip design. - Chih-Yang Peng; Wen-Chang Chao; Yao-Wen Chang; Jyh-Herng Wang (ASP-DAC, 2006)

Novel full-chip gridless routing considering double-via insertion. - Huang-Yu Chen; Mei-Fang Chiang; Yao-Wen Chang; Lumdo Chen; Brian Han (DAC, 2006)

Placement of digital microfluidic biochips using the t-tree formulation. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (DAC, 2006)

A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. - Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (ICCAD, 2006)

An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. - Zhe-Wei Jiang; Yao-Wen Chang (ICCAD, 2006)

Voltage island aware floorplanning for power and timing optimization. - Wan-Ping Lee; Hung-Yi Liu; Yao-Wen Chang (ICCAD, 2006)

Current path analysis for electrostatic discharge protection. - Hung-Yi Liu; Chung-Wei Lin; Szu-Jui Chou; Wei-Ting Tu; Chih-Hung Liu 001; Yao-Wen Chang; Sy-Yen Kuo (ICCAD, 2006)

Inductance extraction for general interconnect structures. - Chun-Ying Lai; Shyh-Kang Jeng; Yao-Wen Chang; Chia-Chun Tsai (ISCAS, 2006)

NTUplace2: a hybrid placer using partitioning and analytical techniques. - Zhe-Wei Jiang; Tung-Chieh Chen; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (ISPD, 2006)

Floorplan and power/ground network co-synthesis for fast design convergence. - Chen-Wei Liu; Yao-Wen Chang (ISPD, 2006)

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. - Bor-Yiing Su; Yao-Wen Chang; Jiang Hu (ISPD, 2006)

Multilevel routing with jumper insertion for antenna avoidance. - Tsung-Yi Ho; Yao-Wen Chang; Sao-Jie Chen (Integr., 2006)

Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. - Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. - Katherine Shu-Min Li; Chauchin Su; Yao-Wen Chang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. - Shang-Wei Tu; Yao-Wen Chang; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Reliable crosstalk-driven interconnect optimization. - Iris Hui-Ru Jiang; Song-Ra Pan; Yao-Wen Chang; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2006)

Full-Chip Nanometer Routing Techniques. - Tsung-Yi Ho; Yao-Wen Chang; Sao-Jie Chen (Springer, 2007)

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. - Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (Modern Circuit Placement, 2007)

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. - Chung-Wei Lin; Ming-Chao Tsai; Kuang-Yao Lee; Tai-Chen Chen; Ting-Chi Wang; Yao-Wen Chang (ASP-DAC, 2007)

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. - Tung-Chieh Chen; Ping-Hung Yuh; Yao-Wen Chang; Fwu-Juh Huang; Denny Liu (DAC, 2007)

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. - Jia-Wei Fang; Chin-Hsiung Hsu; Yao-Wen Chang (DAC, 2007)

A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. - Hung-Yi Liu; Wan-Ping Lee; Yao-Wen Chang (DAC, 2007)

Novel wire density driven full-chip routing for CMP variation control. - Huang-Yu Chen; Szu-Jui Chou; Sheng-Lung Wang; Yao-Wen Chang (ICCAD, 2007)

ECO timing optimization using spare cells. - Yen-Pin Chen; Jia-Wei Fang; Yao-Wen Chang (ICCAD, 2007)

An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. - Wan-Ping Lee; Hung-Yi Liu; Yao-Wen Chang (ICCAD, 2007)

An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. - I-Jye Lin; Yao-Wen Chang (ICCAD, 2007)

Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. - Chung-Wei Lin; Shih-Lun Huang; Kai-Chi Hsu; Meng-Xiang Li; Yao-Wen Chang (ICCAD, 2007)

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ICCAD, 2007)

3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. - Shao-Yi Chien; Chi-Sheng Shih 001; Mong-Kai Ku; Chia-Lin Yang; Yao-Wen Chang; Tei-Wei Kuo; Liang-Gee Chen (ICME, 2007)

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. - Chi-Feng Li; Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ISLPED, 2007)

X-architecture placement based on effective wire models. - Tung-Chieh Chen; Yi-Lin Chuang; Yao-Wen Chang (ISPD, 2007)

Efficient obstacle-avoiding rectilinear steiner tree construction. - Chung-Wei Lin; Szu-Yu Chen; Chi-Feng Li; Yao-Wen Chang; Chia-Lin Yang (ISPD, 2007)

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. - Chin-Hsiung Hsu; Szu-Jui Chou; Jie-Hong Roland Jiang; Yao-Wen Chang (PATMOS, 2007)

Statistical circuit optimization considering device andinterconnect process variations. - I-Jye Lin; Tsui-Yee Ling; Yao-Wen Chang (SLIP, 2007)

X-Route: An X-architecture full-chip multilevel router. - Chen-Feng Chang; Yao-Wen Chang (SoCC, 2007)

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ACM J. Emerg. Technol. Comput. Syst., 2007)

Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. - Tai-Chen Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. - Jia-Wei Fang; I-Jye Lin; Yao-Wen Chang; Jyh-Herng Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. - Hsun-Cheng Lee; Yao-Wen Chang; Hannah Honghua Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Multilevel Full-Chip Routing With Testability and Yield Enhancement. - Katherine Shu-Min Li; Yao-Wen Chang; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. - Chen-Wei Liu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing. - Bor-Yiing Su; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. - Bor-Yiing Su; Yao-Wen Chang; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Temporal floorplanning using the three-dimensional transitive closure subGraph. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2007)

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. - Zhe-Wei Jiang; Bor-Yiing Su; Yao-Wen Chang (DAC, 2008)

A progressive-ILP based routing algorithm for cross-referencing biochips. - Ping-Hung Yuh; Sachin S. Sapatnekar; Chia-Lin Yang; Yao-Wen Chang (DAC, 2008)

Constraint graph-based macro placement for modern mixed-size circuit designs. - Hsin-Chen Chen; Yi-Lin Chuang; Yao-Wen Chang; Yung-Chung Chang (ICCAD, 2008)

Area-I/O flip-chip routing for chip-package co-design. - Jia-Wei Fang; Yao-Wen Chang (ICCAD, 2008)

Routing for chip-package-board co-design considering differential pairs. - Jia-Wei Fang; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2008)

Multi-layer global routing considering via and wire capacities. - Chin-Hsiung Hsu; Huang-Yu Chen; Yao-Wen Chang (ICCAD, 2008)

Effective Wire Models for X-Architecture Placement. - Tung-Chieh Chen; Yi-Lin Chuang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Full-Chip Routing Considering Double-Via Insertion. - Huang-Yu Chen; Mei-Fang Chiang; Yao-Wen Chang; Lumdo Chen; Brian Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. - Tung-Chieh Chen; Yao-Wen Chang; Shyh-Chang Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Metal-Density-Driven Placement for CMP Variation and Routability. - Tung-Chieh Chen; Minsik Cho; David Z. Pan; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. - Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. - Tung-Chieh Chen; Ping-Hung Yuh; Yao-Wen Chang; Fwu-Juh Huang; Tien-Yueh Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. - Zhe-Wei Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. - Chung-Wei Lin; Szu-Yu Chen; Chi-Feng Li; Yao-Wen Chang; Chia-Lin Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. - Chung-Wei Lin; Shih-Lun Huang; Kai-Chi Hsu; Meng-Xiang Lee; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

An Efficient Graph-Based Algorithm for ESD Current Path Analysis. - Chih-Hung Liu 001; Hung-Yi Liu; Chung-Wei Lin; Szu-Jui Chou; Yao-Wen Chang; Sy-Yen Kuo; Shih-Yi Yuan; Yu-Wei Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Packing Floorplan Representations. - Tung-Chieh Chen; Yao-Wen Chang (Handbook of Algorithms for Physical Design Automation, 2008)

Global Interconnect Planning. - Cheng-Kok Koh; Evangeline F. Y. Young; Yao-Wen Chang (Handbook of Algorithms for Physical Design Automation, 2008)

High-performance global routing with fast overflow reduction. - Huang-Yu Chen; Chin-Hsiung Hsu; Yao-Wen Chang (ASP-DAC, 2009)

Flip-chip routing with unified area-I/O pad assignments for package-board co-design. - Jia-Wei Fang; Martin D. F. Wong; Yao-Wen Chang (DAC, 2009)

Spare-cell-aware multilevel analytical placement. - Zhe-Wei Jiang; Meng-Kai Hsu; Yao-Wen Chang; Kai-Yuan Chao (DAC, 2009)

BIST design optimization for large-scale embedded memory cores. - Tzuo-Fan Chien; Wen-Chi Chao; James Chien-Mo Li; Yao-Wen Chang; Kuan-Yu Liao; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng (ICCAD, 2009)

Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. - Wan-Ping Lee; Diana Marculescu; Yao-Wen Chang (ISPD, 2009)

Essential Issues in Analytical Placement Algorithms. - Yao-Wen Chang; Zhe-Wei Jiang; Tung-Chieh Chen (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. - Huang-Yu Chen; Szu-Jui Chou; Sheng-Lung Wang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. - Jia-Wei Fang; Chin-Hsiung Hsu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Voltage-Island Partitioning and Floorplanning Under Timing Constraints. - Wan-Ping Lee; Hung-Yi Liu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Analog Placement Based on Symmetry-Island Formulation. - Mark Po-Hung Lin; Yao-Wen Chang; Shyh-Chang Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. - Ping-Hung Yuh; Sachin S. Sapatnekar; Chia-Lin Yang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

T-trees: A tree-based representation for temporal and three-dimensional floorplanning. - Ping-Hung Yuh; Chia-Lin Yang; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2009)

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. - Paul Falkenstern; Yuan Xie 001; Yao-Wen Chang; Yu Wang 002 (ASP-DAC, 2010)

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. - Xin-Wei Shih; Chung-Chun Cheng; Yuan-Kai Ho; Yao-Wen Chang (ASP-DAC, 2010)

Native-conflict-aware wire perturbation for double patterning technology. - Szu-Yu Chen; Yao-Wen Chang (ICCAD, 2010)

Design-hierarchy aware mixed-size placement for routability optimization. - Yi-Lin Chuang; Gi-Joon Nam; Charles J. Alpert; Yao-Wen Chang; Jarrod A. Roy; Natarajan Viswanathan (ICCAD, 2010)

Redundant-wires-aware ECO timing and mask cost optimization. - Shao-Yun Fang; Tzuo-Fan Chien; Yao-Wen Chang (ICCAD, 2010)

Template-mask design methodology for double patterning technology. - Chin-Hsiung Hsu; Yao-Wen Chang; Sani R. Nassif (ICCAD, 2010)

Recent research development in flip-chip routing. - Hsu-Chieh Lee; Yao-Wen Chang; Po-Wei Lee (ICCAD, 2010)

High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. - Xin-Wei Shih; Hsu-Chieh Lee; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2010)

Efficient provably good OPC modeling and its applications to interconnect optimization. - Shih-Lun Huang; Chung-Wei Lin; Yao-Wen Chang (ICCD, 2010)

Density gradient minimization with coupling-constrained dummy fill for CMP control. - Huang-Yu Chen; Szu-Jui Chou; Yao-Wen Chang (ISPD, 2010)

Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. - Jaw-Luen Tang; Yao-Wen Chang (EURASIP J. Wirel. Commun. Netw., 2010)

Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. - Tai-Chen Chen; Guang-Wan Liao; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. - Jia-Wei Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

ECO Timing Optimization Using Spare Cells and Technology Remapping. - Kuan-Hsien Ho; Yen-Pin Chen; Jia-Wei Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Multilayer Global Routing With Via and Wire Capacity Considerations. - Chin-Hsiung Hsu; Huang-Yu Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips. - Cliff Chiung-Yu Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Simultaneous functional and timing ECO. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2011)

TSV-aware analytical placement for 3D IC designs. - Meng-Kai Hsu; Yao-Wen Chang; Valeriy Balabanov (DAC, 2011)

Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations. - Pang-Yen Chou; Hung-Chih Ou; Yao-Wen Chang (ICCAD, 2011)

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. - Yi-Lin Chuang; Hong-Ting Lin; Tsung-Yi Ho; Yao-Wen Chang; Diana Marculescu (ICCAD, 2011)

Routability-driven analytical placement for mixed-size circuit designs. - Meng-Kai Hsu; Sheng Chou; Tzu-Hen Lin; Yao-Wen Chang (ICCAD, 2011)

A corner stitching compliant B∗-tree representation and its applications to analog placement. - Hui-Fang Tsao; Pang-Yen Chou; Shih-Lun Huang; Yao-Wen Chang; Mark Po-Hung Lin; Duan-Ping Chen; Dick Liu (ICCAD, 2011)

A SAT-based routing algorithm for cross-referencing biochips. - Ping-Hung Yuh; Cliff Chiung-Yu Lin; Tsung-Wei Huang; Tsung-Yi Ho; Chia-Lin Yang; Yao-Wen Chang (SLIP, 2011)

Pulsed-Latch Aware Placement for Timing-Integrity Optimization. - Yi-Lin Chuang; Sangmin Kim; Youngsoo Shin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. - Yi-Lin Chuang; Po-Wei Lee; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Simultaneous Layout Migration and Decomposition for Double Patterning Technology. - Chin-Hsiung Hsu; Yao-Wen Chang; Sani R. Nassif (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips. - Cliff Chiung-Yu Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Thermal-Driven Analog Placement Considering Device Matching. - Mark Po-Hung Lin; Hongbo Zhang 001; Martin D. F. Wong; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Guest Editorial. - Prashant Saxena; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Timing ECO optimization using metal-configurable gate-array spare cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2012)

Structure-aware placement for datapath-intensive circuit designs. - Sheng Chou; Meng-Kai Hsu; Yao-Wen Chang (DAC, 2012)

Simultaneous flare level and flare variation minimization with dummification in EUVL. - Shao-Yun Fang; Yao-Wen Chang (DAC, 2012)

A chip-package-board co-design methodology. - Hsu-Chieh Lee; Yao-Wen Chang (DAC, 2012)

Obstacle-avoiding free-assignment routing for flip-chip designs. - Po-Wei Lee; Hsu-Chieh Lee; Yuan-Kai Ho; Yao-Wen Chang; Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen (DAC, 2012)

Non-uniform multilevel analog routing with matching constraints. - Hung-Chih Ou; Hsing-Chih Chang Chien; Yao-Wen Chang (DAC, 2012)

Statistical thermal modeling and optimization considering leakage power variations. - Da-Cheng Juan; Yi-Lin Chuang; Diana Marculescu; Yao-Wen Chang (DATE, 2012)

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. - Shao-Yun Fang; Szu-Yu Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. - Kuan-Hsien Ho; Jie-Hong Roland Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs. - Meng-Kai Hsu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs. - Chung-Wei Lin; Po-Wei Lee; Yao-Wen Chang; Chin-Fang Shen; Wei-Chih Tseng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Fast Timing-Model Independent Buffered Clock-Tree Synthesis. - Xin-Wei Shih; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Layer minimization in escape routing for staggered-pin-array PCBs. - Yuan-Kai Ho; Xin-Wei Shih; Yao-Wen Chang; Chung-Kuan Cheng (ASP-DAC, 2013)

Symmetrical buffered clock-tree synthesis with supply-voltage alignment. - Xin-Wei Shih; Tzu-Hsuan Hsu; Hsu-Chieh Lee; Yao-Wen Chang; Kai-Yuan Chao (ASP-DAC, 2013)

Double patterning lithography-aware analog placement. - Hsing-Chih Chang Chien; Hung-Chih Ou; Tung-Chieh Chen; Ta-Yu Kuan; Yao-Wen Chang (DAC, 2013)

Multiple chip planning for chip-interposer codesign. - Yuan-Kai Ho; Yao-Wen Chang (DAC, 2013)

Routability-driven placement for hierarchical mixed-size circuit designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Tung-Chieh Chen; Yao-Wen Chang (DAC, 2013)

An efficient and effective analytical placer for FPGAs. - Tzu-Hen Lin; Pritha Banerjee 001; Yao-Wen Chang (DAC, 2013)

Simultaneous analog placement and routing with current flow and current density considerations. - Hung-Chih Ou; Hsing-Chih Chang Chien; Yao-Wen Chang (DAC, 2013)

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. - Shao-Yun Fang; Chung-Wei Lin; Guang-Wan Liao; Yao-Wen Chang (ISPD, 2013)

Circuit placement challenges: technical perspective. - Yao-Wen Chang (Commun. ACM, 2013)

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. - Shao-Yun Fang; Wei-Yu Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Escape Routing for Staggered-Pin-Array PCBs. - Yuan-Kai Ho; Hsu-Chieh Lee; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. - Meng-Kai Hsu; Valeriy Balabanov; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Functional ECO Using Metal-Configurable Gate-Array Spare Cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2014)

Routability-Driven Blockage-Aware Macro Placement. - Yi-Fang Chen; Chau-Chin Huang; Chien-Hsiung Chiou; Yao-Wen Chang; Chang-Jen Wang (DAC, 2014)

A New Asynchronous Pipeline Template for Power and Performance Optimization. - Kuan-Hsien Ho; Yao-Wen Chang (DAC, 2014)

Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. - Chi-Yuan Liu; Hui-Ju Katherine Chiang; Yao-Wen Chang; Jie-Hong R. Jiang (DAC, 2014)

Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. - Yu-Chen Chen; Sheng-Yen Chen; Yao-Wen Chang (ICCAD, 2014)

Simultaneous EUV flare- and CMP-aware placement. - Chi-Yuan Liu; Yao-Wen Chang (ICCD, 2014)

Design and Implementation of a RESTful Notification Service. - Yao-Wen Chang; Ruey-Kai Sheu; Syuan-Ru Jhu; Yue-Shan Chang (ICS, 2014)

Buffered clock tree synthesis considering self-heating effects. - Chung-Wei Lin; Tzu-Hsuan Hsu; Xin-Wei Shih; Yao-Wen Chang (ISLPED, 2014)

A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. - Shao-Yun Fang; Yao-Wen Chang; Wei-Yu Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. - Yuan-Kai Ho; Hsu-Chieh Lee; Webber Lee; Yao-Wen Chang; Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Sheng Chou; Tzu-Hen Lin; Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Nonuniform Multilevel Analog Routing With Matching Constraints. - Hung-Chih Ou; Hsing-Chih Chang Chien; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. - Shao-Yun Fang; Yi-Shu Tai; Yao-Wen Chang (ASP-DAC, 2015)

Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. - Po-Ya Hsu; Yao-Wen Chang (ASP-DAC, 2015)

Detailed-Routing-Driven analytical standard-cell placement. - Chau-Chin Huang; Chien-Hsiung Chiou; Kai-Han Tseng; Yao-Wen Chang (ASP-DAC, 2015)

EUV and e-beam manufacturability: challenges and solutions. - Yao-Wen Chang; Ru-Gun Liu; Shao-Yun Fang (DAC, 2015)

Routing-architecture-aware analytical placement for heterogeneous FPGAs. - Sheng-Yen Chen; Yao-Wen Chang (DAC, 2015)

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography. - Hung-Chih Ou; Kai-Han Tseng; Yao-Wen Chang (DAC, 2015)

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang (ICCAD, 2015)

Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. - Zhi-Wen Lin; Shao-Yun Fang; Yao-Wen Chang; Wei-Cheng Rao; Chieh-Hsiung Kuan (ICCAD, 2015)

Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. - Kuan-Hsien Ho; Hung-Chih Ou; Yao-Wen Chang; Hui-Fang Tsao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Stitch-Aware Routing for Multiple E-Beam Lithography. - Iou-Jen Liu; Shao-Yun Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Circular-contour-based obstacle-aware macro placement. - Chien-Hsiung Chiou; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang (ASP-DAC, 2016)

Recent research development and new challenges in analog layout synthesis. - Mark Po-Hung Lin; Yao-Wen Chang; Chih-Ming Hung (ASP-DAC, 2016)

Timing-driven cell placement optimization for early slack histogram compression. - Chau-Chin Huang; Yen-Chun Liu; Yu-Sheng Lu; Yun-Chih Kuo; Yao-Wen Chang; Sy-Yen Kuo (DAC, 2016)

Minimum-implant-area-aware detailed placement with spacing constraints. - Kai-Han Tseng; Yao-Wen Chang; Charles C. C. Liu (DAC, 2016)

QB-trees: towards an optimal topological representation and its applications to analog layout designs. - I-Peng Wu; Hung-Chih Ou; Yao-Wen Chang (DAC, 2016)

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. - Bo-Qiao Lin; Ting-Chou Lin; Yao-Wen Chang (ICCAD, 2016)

VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology. - Yu-Hsuan Su; Yao-Wen Chang (ICCAD, 2016)

DSA-compliant routing for two-dimensional patterns using block copolymer lithography. - Yu-Hsuan Su; Yao-Wen Chang (ICCAD, 2016)

Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs. - Zhi-Wen Lin; Yao-Wen Chang (ISPD, 2016)

Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. - Hui-Ju Katherine Chiang; Chi-Yuan Liu; Jie-Hong R. Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. - Iou-Jen Liu; Shao-Yun Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Layout-Dependent Effects-Aware Analytical Analog Placement. - Hung-Chih Ou; Kai-Han Tseng; Jhao-Yan Liu; I-Peng Wu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Fast Lithographic Mask Optimization Considering Process Variation. - Yu-Hsuan Su; Yu-Chen Huang; Liang-Chun Tsai; Yao-Wen Chang; Shayak Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

An effective legalization algorithm for mixed-cell-height standard cells. - Chao-Hung Wang; Yen-Yi Wu; Jianli Chen; Yao-Wen Chang; Sy-Yen Kuo; Wenxing Zhu; Genghua Fan (ASP-DAC, 2017)

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. - Jianli Chen; Ziran Zhu; Wenxing Zhu; Yao-Wen Chang (DAC, 2017)

Fogging Effect Aware Placement in Electron Beam Lithography. - Yu-Chen Huang; Yao-Wen Chang (DAC, 2017)

Graph-Based Logic Bit Slicing for Datapath-Aware Placement. - Chau-Chin Huang; Bo-Qiao Lin; Hsin-Ying Lee; Yao-Wen Chang; Kuo-Sheng Wu; Jun-Zhi Yang (DAC, 2017)

Detailed Placement for Two-Dimensional Directed Self-Assembly Technology. - Zhi-Wen Lin; Yao-Wen Chang (DAC, 2017)

A novel damped-wave framework for macro placement. - Chin-Hao Chang; Yao-Wen Chang; Tung-Chieh Chen (ICCAD, 2017)

FPGA placement and routing. - Shih-Chun Chen; Yao-Wen Chang (ICCAD, 2017)

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. - Szu-To Chen; Yao-Wen Chang; Tung-Chieh Chen (ICCAD, 2017)

Clock-aware placement for large-scale heterogeneous FPGAs. - Yun-Chih Kuo; Chau-Chin Huang; Shih-Chun Chen; Chun-Han Chiang; Yao-Wen Chang; Sy-Yen Kuo (ICCAD, 2017)

Redistribution layer routing for wafer-level integrated fan-out package-on-packages. - Ting-Chou Lin; Chia-Chih Chi; Yao-Wen Chang (ICCAD, 2017)

Mixed-cell-height detailed placement considering complex minimum-implant-area constraints. - Yen-Yi Wu; Yao-Wen Chang (ICCAD, 2017)

Blockage-aware terminal propagation for placement wirelength minimization. - Sheng-Wei Yang; Yao-Wen Chang; Tung-Chieh Chen (ICCAD, 2017)

Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement. - Yao-Wen Chang (ISPD, 2017)

An Interview With Professor Chenming Hu, Father of 3D Transistors. - Yao-Wen Chang (IEEE Des. Test, 2017)

Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts. - Zhi-Wen Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Nanowire-Aware Routing Considering High Cut Mask Complexity. - Yu-Hsuan Su; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

WB-trees: a meshed tree representation for FinFET analog layout designs. - Yu-Sheng Lu; Yu-Hsuan Chang; Yao-Wen Chang (DAC, 2018)

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. - Run-Yi Wang; Chia-Cheng Pai; Jun-Jie Wang; Hsiang-Ting Wen; Yu-Cheng Pai; Yao-Wen Chang; James Chien-Mo Li; Jie-Hong Roland Jiang (DAC, 2018)

DSA-friendly detailed routing considering double patterning and DSA template assignments. - Hai-Juan Yu; Yao-Wen Chang (DAC, 2018)

Generalized augmented lagrangian and its applications to VLSI global placement. - Ziran Zhu; Jianli Chen; Zheng Peng 002; Wenxing Zhu; Yao-Wen Chang (DAC, 2018)

Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. - Shih-Chun Chen; Richard Sun; Yao-Wen Chang (ICCAD, 2018)

Novel proximal group ADMM for placement considering fogging and proximity effects. - Jianli Chen; Li Yang; Zheng Peng 002; Wenxing Zhu; Yao-Wen Chang (ICCAD, 2018)

Mixed-cell-height placement with complex minimum-implant-area constraints. - Jianli Chen; Peng Yang; Xingquan Li; Wenxing Zhu; Yao-Wen Chang (ICCAD, 2018)

A multithreaded initial detailed routing algorithm considering global routing guides. - Fan-Keng Sun; Hao Chen; Ching-Yu Chen; Chen-Hao Hsu; Yao-Wen Chang (ICCAD, 2018)

Mixed-cell-height placement considering drain-to-drain abutment. - Yu-Wei Tseng; Yao-Wen Chang (ICCAD, 2018)

Analytical solution of Poisson's equation and its application to VLSI global placement. - Wenxing Zhu; Zhipeng Huang 009; Jianli Chen; Yao-Wen Chang (ICCAD, 2018)

Mixed-cell-height legalization considering technology and region constraints. - Ziran Zhu; Xingquan Li; Yuhang Chen; Jianli Chen; Wenxing Zhu; Yao-Wen Chang (ICCAD, 2018)

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang; Tung-Chieh Chen; Ismail Bustany (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Provably Good Max-Min-m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. - Zhi-Wen Lin; Shao-Yun Fang; Yao-Wen Chang; Wei-Cheng Rao; Chieh-Hsiung Kuan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. - Yen-Chun Liu; Tung-Chieh Chen; Yao-Wen Chang; Sy-Yen Kuo (ASP-DAC, 2019)

BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. - Fan-Keng Sun; Yao-Wen Chang (DAC, 2019)

Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. - Yu-Hsuan Chang; Hsiang-Ting Wen; Yao-Wen Chang (ICCAD, 2019)

Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. - Jianli Chen; Wenxing Zhu; Jun Yu 010; Lei He 001; Yao-Wen Chang (ICCAD, 2019)

Timing-Aware Fill Insertions with Design-Rule and Density Constraints. - Tingshen Lan; Xingquan Li; Jianli Chen; Jun Yu 010; Lei He 001; Senhua Dong; Wenxing Zhu; Yao-Wen Chang (ICCAD, 2019)

Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly. - Zhan-Ling Wang; Yao-Wen Chang (ICCAD, 2019)

Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization. - Xingquan Li; Jianli Chen; Wenxing Zhu; Yao-Wen Chang (ISPD, 2019)

Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging. - Dar-Ren Chen; Yao-Wen Chang; Hwa-Koon Wu; Wei-Chung Shia; Yu-Len Huang (J. Digit. Imaging, 2019)

DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. - Yu-Hsuan Su; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Unified Redistribution Layer Routing for 2.5D IC Packages. - Chun-Han Chiang; Fu-Yu Chuang; Yao-Wen Chang (ASP-DAC, 2020)

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. - Jianli Chen; Zhipeng Huang 009; Ye Huang; Wenxing Zhu; Jun Yu 010; Yao-Wen Chang (DAC, 2020)

Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. - Jianli Chen; Ziran Zhu; Qinghai Liu; Yimin Zhang; Wenxing Zhu; Yao-Wen Chang (DAC, 2020)

Latch Clustering for Timing-Power Co-Optimization. - Chau-Chin Huang; Gustavo E. Téllez; Gi-Joon Nam; Yao-Wen Chang (DAC, 2020)

Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. - Yu-Sheng Lu; Sheng-Jung Yu; Yao-Wen Chang (DAC, 2020)

A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. - Yu-Sheng Lu; Sheng-Jung Yu; Yao-Wen Chang (DAC, 2020)

Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. - Peng Zou; Zhifeng Lin; Xiao Shi; Yingjie Wu; Jianli Chen; Jun Yu 010; Yao-Wen Chang (DAC, 2020)

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (ICCAD, 2020)

Routability-Aware Pin Access Optimization for Monolithic 3D Designs. - Run-Yi Wang; Yao-Wen Chang (ICCAD, 2020)

Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. - Chieh Roger Lo; Teng-Hao Yeh; Wei-Chen Chen; Hang-Ting Lue; Keh-Chung Wang; Chih-Yuan Lu; Yao-Wen Chang; Yung-Hsiang Chen; Chu-Yung Liu (IRPS, 2020)

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. - Jianli Chen; Zhifeng Lin; Yun-Chih Kuo; Chau-Chin Huang; Yao-Wen Chang; Shih-Chun Chen; Chun-Han Chiang; Sy-Yen Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Mixed-Cell-Height Legalization Considering Technology and Region Constraints. - Ziran Zhu; Jianli Chen; Wenxing Zhu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias. - Yu-Jie Cai; Yang Hsu; Yao-Wen Chang (DAC, 2021)

Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems. - Ming-Hung Chen; Yao-Wen Chang; Jun-Jie Wang (DAC, 2021)

VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. - Yun Chou; Jhih-Wei Hsu; Yao-Wen Chang; Tung-Chieh Chen (DAC, 2021)

Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection. - Bingshu Wang; Lanfan Jiang; Wenxing Zhu; Longkun Guo; Jianli Chen; Yao-Wen Chang (DAC, 2021)

Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. - Zhifeng Lin; Yanyue Xie; Gang Qian; Jianli Chen; Sifei Wang; Jun Yu 010; Yao-Wen Chang (DATE, 2021)

On-chip Optical Routing with Waveguide Matching Constraints. - Fu-Yu Chuang; Yao-Wen Chang (ICCAD, 2021)

A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement. - Zih-Yao Lin; Yao-Wen Chang (ICCAD, 2021)

Time-Division Multiplexing Based System-Level FPGA Routing. - Wei-Kai Liu; Ming-Hung Chen; Chia-Ming Chang; Chen-Chia Chang; Yao-Wen Chang (ICCAD, 2021)

Design and implementation of a generic 5G user plane function development framework. - Cheng-Ying Hsieh; Yao-Wen Chang; Chien Chen; Jyh-Cheng Chen (MobiCom, 2021)

Opportunities for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (VLSI-DAT, 2021)

Analytical Placement Considering the Electron-Beam Fogging Effect. - Jianli Chen; Yao-Wen Chang; Yu-Chen Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints. - Jianli Chen; Yao-Wen Chang; Yen-Yi Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. - Chen-Hao Hsu; Shao-Chun Hung; Hao Chen; Fan-Keng Sun; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization. - Jianli Chen; Ziran Zhu; Wenxing Zhu; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2021)

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. - Xiqiong Bai; Ziran Zhu; Peng Zou; Jianli Chen; Jun Yu 010; Yao-Wen Chang (ASP-DAC, 2022)

High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. - Miaodi Su; Hongzhi Ding; Shaohong Weng; Changzhong Zou; Zhonghua Zhou; Yilu Chen; Jianli Chen; Yao-Wen Chang (ASP-DAC, 2022)

Flexible chip placement via reinforcement learning: late breaking results. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (DAC, 2022)

Thermal-aware optical-electrical routing codesign for on-chip signal communications. - Yu-Sheng Lu; Kuan-Cheng Chen; Yu-Ling Hsu; Yao-Wen Chang (DAC, 2022)

Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. - Szu-Ru Nie; Yen-Ting Chen; Yao-Wen Chang (DAC, 2022)

Subgraph matching based reference placement for PCB designs: late breaking results. - Miaodi Su; Yifeng Xiao; Shu Zhang; Haiyuan Su; Jiacen Xu; Huan He; Ziran Zhu; Jianli Chen; Yao-Wen Chang (DAC, 2022)

CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. - Huimin Wang; Xingyu Tong 001; Chenyue Ma; Runming Shi; Jianli Chen; Kun Wang 005; Jun Yu 010; Yao-Wen Chang (DAC, 2022)

High-performance placement for large-scale heterogeneous FPGAs with clock constraints. - Ziran Zhu; Yangjie Mei; Zijun Li 005; Jingwen Lin; Jianli Chen; Jun Yang 006; Yao-Wen Chang (DAC, 2022)

Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. - Yen-Ting Chen; Yao-Wen Chang (ICCAD, 2022)

Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. - Yang Hsu; Min-Hsuan Chung; Yao-Wen Chang; Ci-Hong Lin (ICCAD, 2022)

SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization. - Cheng-Yuan Wang; Yao-Wen Chang; Yuan-Hao Chang 001 (ICCAD, 2022)

Intelligent Design Automation for Heterogeneous Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Charlie Chung-Ping Chen (ISPD, 2022)

Flexible Multiple-Objective Reinforcement Learning for Chip Placement. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (CoRR, 2022)

Timing-Aware Fill Insertions With Design-Rule and Density Constraints. - Xiqiong Bai; Ziran Zhu; Pingping Li; Jianli Chen; Tingshen Lan; Xingquan Li; Jun Yu 010; Wenxing Zhu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects. - Jianli Chen; Zhipeng Huang 009; Ziran Zhu; Zheng Peng 002; Wenxing Zhu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints. - Jianli Chen; Zhifeng Lin; Yanyue Xie; Wenxing Zhu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints. - Jianli Chen; Ziran Zhu; Longkun Guo; Yu-Wei Tseng; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip. - Yu-Sheng Lu; Yan-Lin Chen; Sheng-Jung Yu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment. - Yu-Sheng Lu; Sheng-Jung Yu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Bridge-Based Compression Algorithm for Topological Quantum Circuits. - Wei-Hsiang Tseng; Chen-Hao Hsu; Wan-Hsuan Lin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures. - Hsiang-Ting Wen; Yu-Jie Cai; Yang Hsu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. - Zhijie Cai; Peng Zou; Zhengtao Wu; Xingyu Tong 001; Jun Yu 010; Jianli Chen; Yao-Wen Chang (DAC, 2023)

Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology. - Wei-Hsu Chen; Yao-Wen Chang (DAC, 2023)

Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs. - Kuan-Cheng Chen; Yan-Lin Chen; Yu-Sheng Lu; Yao-Wen Chang (DAC, 2023)

Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies. - Yan-Jen Chen; Yan-Syuan Chen; Wei-Che Tseng; Cheng-Yu Chiang; Yu-Hsiang Lo; Yao-Wen Chang (DAC, 2023)

Any-Angle Routing for Redistribution Layers in 2.5D IC Packages. - Min-Hsuan Chung; Je-Wei Chuang; Yao-Wen Chang (DAC, 2023)

A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints. - Qinghai Liu; Disi Lin; Chuandong Chen; Huan He; Jianli Chen; Yao-Wen Chang (DAC, 2023)

Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. - Qinghai Liu; Qinfei Tang; Jiarui Chen; Chuandong Chen; Ziran Zhu; Huan He; Jianli Chen; Yao-Wen Chang (DAC, 2023)

Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits. - Wei-Hsiang Tseng; Yao-Wen Chang (DAC, 2023)

A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs. - Yan-Lin Chen; Wei-Che Tseng; Wei-Yao Kao; Yao-Wen Chang (ICCAD, 2023)

Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. - Chung-Chia Lee; Yao-Wen Chang (ICCAD, 2023)

Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks. - Jhih-Wei Hsu; Kuan-Cheng Chen; Yan-Syuan Chen; Yu-Hsiang Lo; Yao-Wen Chang (ISPD, 2023)

Analytical Solution of Poisson's Equation with Application to VLSI Global Placement. - Wenxing Zhu; Zhipeng Huang 009; Jianli Chen; Yao-Wen Chang (CoRR, 2023)

What attracts young talent from Taiwan to start businesses in mainland China? A fuzzy analytic hierarchy process study. - Yao-Wen Chang; Yi-Hsuan Lai (Technol. Anal. Strateg. Manag., 2023)

Routability-driven Power/Ground Network Optimization Based on Machine Learning. - Ping-Wei Huang; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2023)

Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. - Min Wei; Xingyu Tong 001; Yuan Wen; Jianli Chen; Jun Yu 010; Wenxing Zhu; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2023)

Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes. - Yan-Jen Chen; Cheng-Hsiu Hsieh; Po-Han Su; Shao-Hsiang Chen; Yao-Wen Chang (DAC, 2024)

Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures. - Je-Wei Chuang; Zong-Han Wu; Bo-Ying Huang; Yao-Wen Chang (DAC, 2024)

Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards. - Wei-Che Tseng; Zong-Ying Cai; Yi-Ping Huang; Yu-Hsiang Lo; Yao-Wen Chang (DAC, 2024)

Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints. - Chien-Hao Tsou; Sheng-Yah Lin; Wei-Chen Hung; Yao-Wen Chang (DAC, 2024)

Electrostatics-Based Analytical Global Placement for Timing Optimization. - Zhifeng Lin; Min Wei; Yilu Chen; Peng Zou; Jianli Chen; Yao-Wen Chang (DATE, 2024)

Efficient High-Fidelity Two-Dimensional Warpage Modeling for Advanced Packaging Analysis. - Shao-Yu Lo; MaoZe Liu; Yao-Wen Chang (ICCAD, 2024)

Physical Design Challenges in Modern Heterogeneous Integration. - Yao-Wen Chang (ISPD, 2024)

Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems. - Wei-Hsiang Tseng; Yao-Wen Chang; Jie-Hong Roland Jiang (ISPD, 2024)

A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits. - Wei-Hsiang Tseng; Yao-Wen Chang (ACM Trans. Design Autom. Electr. Syst., 2024)

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. - Ziran Zhu; Yangjie Mei; Kangkang Deng; Huan He; Jianli Chen; Jun Yang 006; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Subgraph matching-based reference placement for printed circuit board designs. - Ziran Zhu; Yilin Li; Miaodi Su; Shu Zhang; Haiyuan Su; Yifeng Xiao; Huan He; Jianli Chen; Yao-Wen Chang (J. Supercomput., 2024)

Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. - Cheng-Yu Chiang; Yi-Hsien Chiang; Chao-Chi Lan; Yang Hsu; Che-Ming Chang; Shao-Chi Huang; Sheng-Hua Wang; Yao-Wen Chang; Hung-Ming Chen (ASP-DAC, 2025)

Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models. - Wei-Yao Kao; Tai-Jung Lin; Yao-Wen Chang (ASP-DAC, 2025)

Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine Learning. - Chao-Chi Lan; Chuan-Chi Su; Yuan-Hsiang Lu; Yao-Wen Chang (ASP-DAC, 2025)