A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity. - Yao Xin; Will X. Y. Li; Biao Min; Yan Han; Ray C. C. Cheung (EMBC, 2013)

Erratum to "Finding the most efficient DMUs in DEA: An improved integrated model" [Comput. Indus. Eng. 52 (2007) 71-77]. - Yan Q. You; Tao Jie; Yao Xin (Comput. Ind. Eng., 2013)

Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform. - Yao Xin; Benben Liu; Biao Min; Will X. Y. Li; Ray C. C. Cheung; Anthony S. Fong; Ting-Fung Chan (Microelectron. J., 2013)

Laguerre-volterra model and architecture for MIMO system identification and output prediction. - Will X. Y. Li; Yao Xin; Rosa H. M. Chan; Dong Song; Theodore W. Berger; Ray C. C. Cheung (EMBC, 2014)

VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel. - Will X. Y. Li; Yao Xin; Dong Song; Theodore W. Berger; Ray C. C. Cheung (ISIC, 2014)

GPU-based biclustering for microarray data analysis in neurocomputing. - Benben Liu; Yao Xin; Ray C. C. Cheung; Hong Yan 001 (Neurocomputing, 2014)

An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking. - Yao Xin; Will X. Y. Li; Ray C. C. Cheung; Rosa H. M. Chan; Hong Yan 001; Dong Song; Theodore W. Berger (Microelectron. J., 2014)

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics. - Yao Xin; Will X. Y. Li; Zhaorui Zhang; Ray C. C. Cheung; Dong Song; Theodore W. Berger (IEEE ACM Trans. Comput. Biol. Bioinform., 2015)

FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery. - Zhaorui Zhang; Yao Xin; Benben Liu; Will X. Y. Li; Kit-Hang Lee; Chun-Fai Ng; Danail Stoyanov; Ray C. C. Cheung; Ka-Wai Kwok (Frontiers Robotics AI, 2016)

An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis. - Will X. Y. Li; Ray C. C. Cheung; Yao Xin; Dong Song; Theodore W. Berger (J. Circuits Syst. Comput., 2016)

KickTree: A Recursive Algorithmic Scheme for Packet Classification with Bounded Worst-Case Performance. - Yao Xin; Yuxi Liu; Wenjun Li 004; Ruyi Yao; Yang Xu 010; Yi Wang 004 (ANCS, 2021)

An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets. - Yao Xin; Wenjun Li 004; Yi Wang 004; Song Yao (INFOCOM Workshops, 2021)

HybridTSS: A Recursive Scheme Combining Coarse- and Fine- Grained Tuples for Packet Classification. - Yuxi Liu; Yao Xin; Wenjun Li 004; Haoyu Song 001; Ori Rottenstreich; Gaogang Xie; Weichao Li 001; Yi Wang 004 (APNet, 2022)

Updatable Packet Classification on FPGA with Bounded Worst-Case Performance. - Yao Xin; Wenjun Li 004; Gaogang Xie; Yang Xu 010; Yi Wang 004 (HOTI, 2022)

A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection. - Yao Xin; Guoming Tang; Donglong Chen; Rumin Zhang; Teng Liang; Ray C. C. Cheung; Çetin Kaya Koç (SmartWorld/UIC/ScalCom/DigitalTwin/PriComp/Meta, 2022)

High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection. - Yao Xin; Donald Donglong Chen; Chongyang Zeng; Weichen Zhang; Yi Wang 004; Ray C. C. Cheung (IEEE Trans. Computers, 2022)

FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree. - Yao Xin; Wenjun Li 004; Guoming Tang; Tong Yang 003; Xiaohe Hu; Yi Wang 004 (IEEE/ACM Trans. Netw., 2022)

Comparative analysis of neural networks techniques to forecast Airfare Prices. - Alessandro Aliberti; Yao Xin; Alessio Viticchié; Enrico Macii; Edoardo Patti (COMPSAC, 2023)

Building a High-Performance Data Channel for the Federal Cyber Range. - Zengxie Ma; Ning Hu; Bo Qu; Yao Xin; Shengan Song; Xinyi Qiu (DSC, 2023)

MCCQF: Low-Latency Transmission Based on IEEE 802.1 Qch For Hierarchical Networking. - Yan Liu 062; Dajun Zhou; Shuangping Zhan; Yao Xin; Jiashuo Lin; Xingbo Feng; Enze Shi; Ye Qi; Gang Chen; Junqing Zheng; Yi Wang; Xiao Zheng (ICC, 2023)

A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets. - Yao Xin; Wenjun Li 004; Gaogang Xie; Yang Xu 010; Yi Wang 004 (IEEE Micro, 2023)

Bubble Sketch: A High-performance and Memory-efficient Sketch for Finding Top-k Items in Data Streams. - Lu Cao; Qilong Shi; Yuxi Liu; Hanyue Zheng; Yao Xin; Wenjun Li 004; Tong Yang 003; Yangyang Wang 001; Yang Xu 010; Weizhe Zhang; Mingwei Xu (CIKM, 2024)

A novel low-latency scheduling approach of TSN for multi-link rate networking. - Xiao Zheng; Yan Liu 062; Shuangping Zhan; Yao Xin; Yi Wang (Comput. Networks, 2024)

Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA. - Yao Xin; Wenjun Li 004; Chengjun Jia; Xianfeng Li; Yang Xu 010; Bin Liu 001; Zhihong Tian; Weizhe Zhang (IEEE/ACM Trans. Netw., 2024)

Reversible data hiding in Redundancy-Free cipher images through pixel rotation and multi-MSB replacement. - Lingfeng Qu; Xu Wang 027; Yuan Yuan 038; Jiayu Zhou; Yao Xin (J. Inf. Secur. Appl., 2025)

A Heterogeneous and Adaptive Architecture for Decision-Tree-Based ACL Engine on FPGA. - Yao Xin; Chengjun Jia; Wenjun Li 004; Ori Rottenstreich; Yang Xu 010; Gaogang Xie; Zhihong Tian; Jun Li 002 (IEEE Trans. Computers, 2025)

CLLoRA: An Approach to Measure the Effects of the Context Length for LLM Fine-Tuning. - Ping Zhang; Zhaorui Zhang; Sheng Di; Yao Xin; Benben Liu (CoRR, 2025)

ERPC: Efficient Rule Partitioning Through Community Detection for Packet Classification. - Jinshui Wang; Yao Xin; Chongwu Dong; Lingfeng Qu; Yiming Ding (IEEE Trans. Netw. Serv. Manag., 2025)