Workspace analysis of a novel 6-dof cable-driven parallel robot. - Yaojun Zhang; Yuru Zhang; Xiaowei Dai; Yi Yang (ROBIO, 2009)

The analysis of resolution for cable-driven haptic device. - Hao Hu; Yuru Zhang; Xiaowei Dai; Yaojun Zhang (ROBIO, 2010)

STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. - Yaojun Zhang; Xiaobin Wang; Yiran Chen 001 (ICCAD, 2011)

Probabilistic design in spintronic memory and logic circuit. - Yiran Chen 001; Yaojun Zhang; Peiyuan Wang (ASP-DAC, 2012)

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. - Wujie Wen; Yaojun Zhang; Yiran Chen 001; Yu Wang 002; Yuan Xie 001 (DAC, 2012)

Asymmetry of MTJ switching and its implication to STT-RAM designs. - Yaojun Zhang; Xiaobin Wang; Yong Li 009; Alex K. Jones; Yiran Chen 001 (DATE, 2012)

Multi-level cell STT-RAM: Is it realistic or just a dream? - Yaojun Zhang; Lu Zhang; Wujie Wen; Guangyu Sun 003; Yiran Chen 001 (ICCAD, 2012)

Improving energy efficiency of write-asymmetric memories by log style write. - Guangyu Sun 003; Yaojun Zhang; Yu Wang 002; Yiran Chen 001 (ISLPED, 2012)

iFeel6-BH1500: A large-scale 6-DOF haptic device. - Zhongyuan Chen; Yuru Zhang; Dangxiao Wang; Chaobin Li; Yaojun Zhang (VECIMS, 2012)

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. - Yong Li 009; Yaojun Zhang; Yiran Chen 001; Alex K. Jones (IEEE Embed. Syst. Lett., 2012)

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. - Zhenyu Sun 001; Xiang Chen 010; Yaojun Zhang; Hai Li 001; Yiran Chen 001 (ACM J. Emerg. Technol. Comput. Syst., 2012)

Loadsa: A yield-driven top-down design method for STT-RAM array. - Wujie Wen; Yaojun Zhang; Lu Zhang; Yiran Chen 001 (ASP-DAC, 2013)

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. - Jie Guo 002; Wujie Wen; Yaojun Zhang; Sicheng Li 001; Hai Li 001; Yiran Chen 001 (DATE, 2013)

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. - Yaojun Zhang; Ismail Bayram; Yu Wang 002; Hai Li 001; Yiran Chen 001 (ICCAD, 2013)

Pseudo-Three-Dimensional Navigation in Helical Scan Security Inspection. - Bin Li; Baolei Li; Yang Mo; Yaojun Zhang (ICIG, 2013)

MLC STT-RAM design considering probabilistic and asymmetric MTJ switching. - Yaojun Zhang; Lu Zhang; Yiran Chen 001 (ISCAS, 2013)

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. - Yiran Chen 001; Weng-Fai Wong; Hai Li 001; Cheng-Kok Koh; Yaojun Zhang; Wujie Wen (ACM J. Emerg. Technol. Comput. Syst., 2013)

C1C: A configurable, compiler-guided STT-RAM L1 cache. - Yong Li 009; Yaojun Zhang; Hai Li 001; Yiran Chen 001; Alex K. Jones (ACM Trans. Archit. Code Optim., 2013)

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. - Xiaoxiao Liu 001; Yong Li 009; Yaojun Zhang; Alex K. Jones; Yiran Chen 001 (ASP-DAC, 2014)

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. - Enes Eken; Yaojun Zhang; Wujie Wen; Rajiv V. Joshi; Hai Li 001; Yiran Chen 001 (DAC, 2014)

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. - Mengjie Mao; Wujie Wen; Yaojun Zhang; Yiran Chen 001; Hai (Helen) Li (DAC, 2014)

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. - Wujie Wen; Yaojun Zhang; Mengjie Mao; Yiran Chen 001 (DAC, 2014)

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. - Wujie Wen; Yaojun Zhang; Yiran Chen 001; Yu Wang 002; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Recent progresses of STT memory design and applications. - Bonan Yan; Yaojun Zhang; Enes Eken; Wujie Wen; Weisheng Zhao; Yiran Chen 001 (ASICON, 2015)

Giant spin hall effect (GSHE) logic design for low power application. - Yaojun Zhang; Bonan Yan; Wenqing Wu; Hai Li 001; Yiran Chen 001 (DATE, 2015)

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. - Bonan Yan; Zheng Li; Yaojun Zhang; Jianlei Yang 001; Hai Li 001; Weisheng Zhao; Pierre Chor-Fung Chia (ACM Great Lakes Symposium on VLSI, 2015)

Read Performance: The Newest Barrier in Scaled STT-RAM. - Yaojun Zhang; Yong Li 009; Zhenyu Sun 001; Hai Li 001; Yiran Chen 001; Alex K. Jones (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A novel PUF based on cell error rate distribution of STT-RAM. - Xian Zhang 001; Guangyu Sun 003; Yaojun Zhang; Yiran Chen 001; Hai Li 001; Wujie Wen; Jia Di (ASP-DAC, 2016)

Spin-Hall Assisted STT-RAM Design and Discussion. - Enes Eken; Ismail Bayram; Yaojun Zhang; Bonan Yan; Wenqing Wu; Hai (Helen) Li; Yiran Chen 001 (SLIP, 2016)

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. - Jianlei Yang 001; Peiyuan Wang; Yaojun Zhang; Yuanqing Cheng; Weisheng Zhao; Yiran Chen 001; Hai (Helen) Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Giant Spin-Hall assisted STT-RAM and logic design. - Enes Eken; Ismail Bayram; Yaojun Zhang; Bonan Yan; Wenqing Wu; Hai (Helen) Li; Yiran Chen 001 (Integr., 2017)

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. - Mengjie Mao; Wujie Wen; Yaojun Zhang; Yiran Chen 001; Hai Li 001 (IEEE Trans. Computers, 2017)

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. - Yaojun Zhang; Bonan Yan; Xiaobin Wang; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. - Bonan Yan; Fan Chen 001; Yaojun Zhang; Chang Song 001; Hai Li 001; Yiran Chen 001 (DATE, 2018)

Stock Market Prediction Model Based on LSTM Deep Learning: The Case of Top Corporate Company in China. - Yaojun Zhang; Gilbert M. Tumibay (AIAM, 2022)

Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. - Kangyi Qiu; Yaojun Zhang; Bonan Yan; Ru Huang 001 (ASP-DAC, 2022)

A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. - Bonan Yan; Jeng-Long Hsu; Pang-Cheng Yu; Chia-Chi Lee; Yaojun Zhang; Wenshuo Yue; Guoqiang Mei; Yuchao Yang 001; Yue Yang; Hai Li 001; Yiran Chen 001; Ru Huang 001 (ISSCC, 2022)

Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System. - Anjunyi Fan; Bo Hu; Zhonghua Jin; Haiyue Han; Yaojun Zhang; Yue Yang; Yuchao Yang 001; Bonan Yan; Ru Huang 001 (AICAS, 2023)

SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization. - Yanjun Li; Chunshan Zu; Bingqian Wang; Zhenhua Zhu; Yaojun Zhang; Ran Duan; Bing Li 017; Bonan Yan (ACM Great Lakes Symposium on VLSI, 2023)

Bayesian CART models for insurance claims frequency. - Yaojun Zhang; Lanpeng Ji; Georgios Aivaliotis; Charles Taylor (CoRR, 2023)

Hadamard product-based in-memory computing design for floating point neural network training. - Anjunyi Fan; Yihan Fu; Yaoyu Tao; Zhonghua Jin; Haiyue Han; Huiyu Liu; Yaojun Zhang; Bonan Yan; Yuchao Yang 001; Ru Huang 001 (Neuromorph. Comput. Eng., 2023)

Exploring the Relationships between Land Surface Temperature and Its Influencing Factors Using Multisource Spatial Big Data: A Case Study in Beijing, China. - Xiaoxi Wang; Yaojun Zhang; Danlin Yu (Remote. Sens., 2023)

Bayesian CART models for aggregate claim modeling. - Yaojun Zhang; Lanpeng Ji; Georgios Aivaliotis; Charles C. Taylor (CoRR, 2024)

Maintainability analysis and comprehensive tradeoff of naval ships equipment based on PROMETHEE method. - Shanshan Zheng; Guofeng Chen; Yaojun Zhang (J. Control. Decis., 2024)

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. - Ruiqi Guo; Zhiheng Yue; Yang Wang 089; Hao Li; Te Hu; Yabing Wang; Hao Sun; Jeng-Long Hsu; Yaojun Zhang; Bonan Yan; Leibo Liu; Ru Huang 001; et al. (IEEE J. Solid State Circuits, 2025)

A novel framework for fully-automated co-registration of intravascular ultrasound and optical coherence tomography imaging data. - Xingwei He 007; Kit Mills Bransby; Ahmet Emir Ulutas; Thamil Kumaran; Nathan Angelo Lecaros Yap; Gonul Zeren; Hesong Zeng; Yaojun Zhang; Andreas Baumbach; James Moon; Anthony Mathur; Jouke Dijkstra; et al. (CoRR, 2025)