A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation. - Hedi Wang; Zengwei Wang; Yaolei Li; Chen Tang; Jinxu Gao; Huazhong Yang; Yongpan Liu (A-SSCC, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. - Yaolei Li; Jinshan Yue; Jingyu Wang 004; Chen Tang; Yifan He 003; Wenbin Jia; Kaiwei Zou; Lu Zhang; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array. - Lu Zhang; Dejun Mu; Yuxuan Huang; Jingyu Wang 004; Yifan He 003; Yaolei Li; Lizhou Liu; Kaiwei Zou; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. - Yifan He 003; Shupei Fan; Xuan Li; Luchang Lei; Wenbin Jia; Chen Tang; Yaolei Li; Zongle Huang; Zhike Du; Jinshan Yue; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2024)

RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel. - Lu Zhang; Dejun Mu; Jingyu Wang 004; Ruoyang Liu; Yifan He 003; Yaolei Li; Yu Tai; Shengbing Zhang; Xiaoya Fan; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks. - Wenbin Jia; Yifan He 003; Xiang Li; Yixuan Xie; Zongle Huang; Wenxun Wang; Boju Chen; Yaolei Li; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; et al. (CICC, 2025)