High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. - Yaoyu Tao; Youn Sung Park; Zhengya Zhang (ISCAS, 2012)

Efficient in situ error detection enabling diverse path coverage. - Chia-Hsiang Chen; Yaoyu Tao; Zhengya Zhang (ISCAS, 2013)

A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. - Youn Sung Park; Yaoyu Tao; Zhengya Zhang (ISSCC, 2013)

A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. - Youn Sung Park; Yaoyu Tao; Shuanghong Sun; Zhengya Zhang (VLSIC, 2014)

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. - Youn Sung Park; Yaoyu Tao; Zhengya Zhang (IEEE J. Solid State Circuits, 2015)

An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes. - Yaoyu Tao; Qi Wu (ISCAS, 2019)

A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. - Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang (VLSI Circuits, 2019)

Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. - Yaoyu Tao; Shuanghong Sun; Zhengya Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

DNC-Aided SCL-Flip Decoding of Polar Codes. - Yaoyu Tao; Zhengya Zhang (GLOBECOM, 2021)

HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. - Yaoyu Tao; Zhengya Zhang (MICRO, 2021)

A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. - Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder. - Yaoyu Tao; Cedric Choi (ISCAS, 2022)

Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm. - Lianfeng Yu; Zhaokun Jing; Yuchao Yang 001; Yaoyu Tao (ISCAS, 2022)

Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search. - Lei Cai; Jing Wang 172; Lianfeng Yu; Bonan Yan; Yaoyu Tao; Yuchao Yang 001 (FPGA, 2023)

eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs. - Junkang Zhu; Yaoyu Tao; Zhengya Zhang (HPCA, 2023)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

Fast and reconfigurable sort-in-memory system enabled by memristors. - Lianfeng Yu; Yaoyu Tao; Teng Zhang; Zeyu Wang; Xile Wang; Zelun Pan; Bowen Wang; Zhaokun Jing; Jiaxin Liu; Yuqi Li; Yihang Zhu; Bonan Yan; et al. (CoRR, 2023)

Hadamard product-based in-memory computing design for floating point neural network training. - Anjunyi Fan; Yihan Fu; Yaoyu Tao; Zhonghua Jin; Haiyue Han; Huiyu Liu; Yaojun Zhang; Bonan Yan; Yuchao Yang 001; Ru Huang 001 (Neuromorph. Comput. Eng., 2023)

MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads. - Yihang Zhu; Lei Cai; Lianfeng Yu; Anjunyi Fan; Longhao Yan; Zhaokun Jing; Bonan Yan; Pek Jun Tiw; Yuqi Li; Yaoyu Tao; Yuchao Yang 001 (MICRO, 2024)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)

PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference. - Yihan Fu; Anjunyi Fan; Wenshuo Yue; Hongxiao Zhao; Daijing Shi; Qiuping Wu; Jiayi Li; Xiangyu Zhang; Yaoyu Tao; Yuchao Yang 001; Bonan Yan (HPCA, 2025)

Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory. - Daijing Shi; Yihang Zhu; Anjunyi Fan; Yaoyu Tao; Yuchao Yang 001; Bonan Yan (CoRR, 2025)