A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Yoshiyasu Tanamura; Ryoichi Yamashita; Hiroyuki Sugiyama; Yaroku Sugiyama; Hirofumi Hamamura (ICCD, 2003)

Detection of multiple transitions in delay fault test of SPARC64 microprocessor. - Daisuke Maruyama; Akira Kanuma; Takashi Mochiyama; Hiroaki Komatsu; Yaroku Sugiyama; Noriyuki Ito (ICCAD, 2004)

Delay defect screening for a 2.16GHz SPARC64 microprocessor. - Noriyuki Ito; Akira Kanuma; Daisuke Maruyama; Hitoshi Yamanaka; Tsuyoshi Mochizuki; Osamu Sugawara; Chihiro Endoh; Masahiro Yanagida; Takeshi Kono; Yutaka Isoda; Kazunobu Adachi; Takahisa Hiraide; et al. (ASP-DAC, 2006)

Diagonal routing in high performance microprocessor design. - Noriyuki Ito; Hideaki Katagiri; Ryoichi Yamashita; Hiroshi Ikeda; Hiroyuki Sugiyama; Hiroaki Komatsu; Yoshiyasu Tanamura; Akihiro Yoshitake; Kazuhiro Nonomura; Kinya Ishizaka; Hiroaki Adachi; Yutaka Mori; et al. (ASP-DAC, 2006)