Power Macromodeling for IP Modules. - Yaseer Arafat Durrani; Teresa Riesgo (ICECS, 2006)

Power estimation for register transfer level by genetic algorithm. - Yaseer Arafat Durrani; Teresa Riesgo; Felipe Machado (ICINCO-RA, 2006)

Power Estimation for IP-Based Modules. - Yaseer Arafat Durrani; Teresa Riesgo (SoC, 2006)

Power Macromodeling for High Level Power Estimation. - Yaseer Arafat Durrani; Teresa Riesgo (ReCoSoC, 2006)

LUT-Based Power Macromodeling Technique for DSP Architectures. - Yaseer Arafat Durrani; Teresa Riesgo (ICECS, 2007)

Efficient Power Macromodeling Technique for IP-Based Digital System. - Yaseer Arafat Durrani; Ana Abril; Teresa Riesgo (ISCAS, 2007)

Architectural Power Analysis for Intellectual Property-Based Digital System. - Yaseer Arafat Durrani; Teresa Riesgo (J. Low Power Electron., 2007)

Power estimation technique for DSP architectures. - Yaseer Arafat Durrani; Teresa Riesgo (Digit. Signal Process., 2009)

Efficient power macromodeling technique for conventional MOS transistors. - Yaseer Arafat Durrani (ICEEI, 2011)

High-Level Power Analysis for Intellectual Property-Based Digital Systems. - Yaseer Arafat Durrani; Teresa Riesgo (Circuits Syst. Signal Process., 2014)

Power estimation for intellectual property-based digital systems at the architectural level. - Yaseer Arafat Durrani; Teresa Riesgo (J. King Saud Univ. Comput. Inf. Sci., 2014)

Efficient power analysis approach and its application to system-on-chip design. - Yaseer Arafat Durrani; Teresa Riesgo (Microprocess. Microsystems, 2016)

Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs. - Yaseer Arafat Durrani (J. Circuits Syst. Comput., 2018)

Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm. - Faisal Siddiq; Yaseer Arafat Durrani (Turkish J. Electr. Eng. Comput. Sci., 2021)