Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation. - Yashrajsinh Parmar; K. Sridharan 001 (IECON, 2018)

Precomputation-based radix-4 CORDIC for approximate rotations and Hough transform. - Yashrajsinh Parmar; Krishnamurthy Sridharan (IET Circuits Devices Syst., 2018)

A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks. - Yashrajsinh Parmar; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A High-Performance VLSI Architecture for a Self-Feedback Convolutional Neural Network. - Yashrajsinh Parmar; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)