An Implementation of Handshake Join on FPGA. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (ICNC, 2011)

Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (MCSoC, 2012)

Design and Implementation of a Handshake Join Architecture on FPGA. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2012)

An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. - Yasin Oge; Masato Yoshimi; Takefumi Miyoshi; Hideyuki Kawashima; Hidetsugu Irie; Tsutomu Yoshinaga (CANDAR, 2013)

A fast handshake join implementation on FPGA with adaptive merging network. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (SSDBM, 2013)

Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage. - Masato Yoshimi; Ryu Kudo; Yasin Oge; Yuta Terada; Hidetsugu Irie; Tsutomu Yoshinaga (CANDAR, 2014)

An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications. - Masato Yoshimi; Ryu Kudo; Yasin Oge; Yuta Terada; Hidetsugu Irie; Tsutomu Yoshinaga (MCSoC, 2014)

Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. - Yasin Oge; Masato Yoshimi; Takefumi Miyoshi; Hideyuki Kawashima; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2015)

Pipelined Parallel Join and Its FPGA-Based Acceleration. - Masato Yoshimi; Yasin Oge; Tsutomu Yoshinaga (ACM Trans. Reconfigurable Technol. Syst., 2017)

Software-Based Time-Aware Shaper for Time-Sensitive Networks. - Yasin Oge; Yuta Kobayashi; Takahiro Yamaura; Tomonori Maegawa (IEICE Trans. Commun., 2020)