Low-delay parallel Chien search architecture for RS decoder. - Xiaoqiang Zhang 001; Ning Wu; Fang Zhou 001; Jianhua Li; Yasir Khizar (IEICE Electron. Express, 2016)

FPGA based highly efficient MISTY1 architecture. - Yasir Khizar; Ning Wu; Xin Chen 039; Muhammad Rehan Yahya; Xiaoqiang Zhang 001 (IEICE Electron. Express, 2017)

Compact Hardware Implementations of MISTY1 Block Cipher. - Yasir Khizar; Ning Wu; Xiaoqiang Zhang 001 (J. Circuits Syst. Comput., 2018)

An Algorithmic Framework to Construct Optical Switch via Scaling From N-to-2N Ports for Optical Network on Chip. - Muhammad Rehan Yahya; Ning Wu; Gaizhen Yan; Tanveer Ahmed; Yasir; Jinbao Zhang 002 (IEEE Access, 2019)

Compact and High Speed Architectures of KASUMI Block Cipher. - Yasir Khizar; Ning Wu; Zain Anwar Ali; Muhammad Mujtaba Shaikh 001; Muhammad Rehan Yahya; Muhammad Aamir 001 (Wirel. Pers. Commun., 2019)

Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore Processors. - Muhammad Rehan Yahya; Ning Wu; Zain Anwar Ali; Yasir Khizar (Wirel. Pers. Commun., 2021)