Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects. - Takeshi Nogami; Oleg Gluschenkov; Yasir Sulehria; Son Nguyen; Brown Peethala; Huai Huang; Hosadurga Shobha; Nick A. Lanzillo; Raghuveer Patlolla; Devika Sil; Andrew Simon; Daniel Edelstein; et al. (VLSI Technology and Circuits, 2022)

Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type Devices. - Huimei Zhou; Miaomiao Wang 006; Nicolas Loubet; Andrew Gaul; Yasir Sulehria (IRPS, 2023)

Backside Power Distribution for Nanosheet Technologies Beyond 2nm. - Ruilong Xie; Wonhyuk Hong; Chen Zhang; Jongjin Lee; Kevin Brew; Richard Johnson; Nicholas A. Lanzillo; Hosadurga Shobha; Taesun Kim; Panjae Park; Shogo Mochizuki; Iqbal Saraf; et al. (VLSI Technology and Circuits, 2024)

Hot Carrier Degradation and performance boost on Si Channel nFET Gate-All-Around Nanosheet Devices. - H. Zhou; M. Hasanuzzaman; S. D. Suk; S. Emans; S. Siddiqui; R. Robison; R. Vega; M. Wang; Yasir Sulehria; S. Mochizuki; C. Durfee; Oleg Gluschenkov; et al. (IRPS, 2025)