Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. - Renyu Yang; Junzhong Shen; Mei Wen; Yasong Cao; Yuhang Li (HPCC/DSS/SmartCity/DependSys, 2021)

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. - Yasong Cao; Mei Wen; Junzhong Shen; Sheng Liu 001; Zhi Wang; Minjin Tang; Yahao Fang; Jianchao Yang; Renyu Yang; Yuhan Kang; Jiawei Fei (HPCC/DSS/SmartCity/DependSys, 2022)

BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. - Jianchao Yang; Mei Wen; Junzhong Shen; Yasong Cao; Minjin Tang; Renyu Yang; Jiawei Fei; Chunyuan Zhang (ICCD, 2022)

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. - Minjin Tang; Mei Wen; Yasong Cao; Junzhong Shen; Jianchao Yang; Jiawei Fei; Yang Guo 003; Sheng Liu 001 (ICPP, 2022)

S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. - Yuhang Li; Mei Wen; Renyu Yang; Junzhong Shen; Yasong Cao; Jianan Wang (ISCAS, 2022)

TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. - Yuhang Li; Mei Wen; Jiawei Fei; Junzhong Shen; Yasong Cao (ISPASS, 2022)

BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM. - Yasong Cao; Mei Wen; Junzhong Shen; Zhongxing Li (ASAP, 2024)

ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core. - Yasong Cao; Mei Wen; Zhongdi Luo; Xin Ju 005; Haolan Huang; Junzhong Shen; Haiyan Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point. - Xin Ju 005; Jun He; Mei Wen; Jing Feng; Yasong Cao; Junzhong Shen; Zhaoyun Chen; Yang Shi 008 (DATE, 2025)

SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity. - Jingkui Yang; Mei Wen; Junzhong Shen; Jianchao Yang; Yasong Cao; Jun He; Minjin Tang; Zhaoyun Chen; Yang Shi 008 (DATE, 2025)