Design methodologies for high-performance noise-tolerant XOR-XNOR circuits. - Sumeer Goel; Mohamed A. Elgamel; Magdy A. Bayoumi; Yasser Y. Hanafy (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Enhanced mobile node's reachability through anycasting for MIPv6 regional registrations. - Ayman Abdel-Hamid; Lobna Eslim; Yasser Y. Hanafy (AICCSA, 2008)

Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures. - Amr M. Bayoumi; Yasser Y. Hanafy (IFMT, 2008)

Scientific and Engineering Computing Using ATI Stream Technology. - Amr M. Bayoumi; Michael Chu; Yasser Y. Hanafy; Patricia Harrell; Gamal Refai-Ahmed (Comput. Sci. Eng., 2009)

NOA'S-Arc: NISC based, optimized array scalable architecture. - Mohamed Wasfy Hassan; Ahmed A. Abouel Farag; Yasser Y. Hanafy (MWSCAS, 2013)

Parallel circuit simulation using the direct method on a heterogeneous cloud. - Ahmed E. Helal; Amr M. Bayoumi; Yasser Y. Hanafy (DAC, 2015)

High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow Model. - Mohamed W. Hassan; Ahmed E. Helal; Yasser Y. Hanafy (FCCM, 2015)

AutoMatch: An automated framework for relative performance estimation and workload distribution on heterogeneous HPC systems. - Ahmed E. Helal; Wu-chun Feng; Changhee Jung; Yasser Y. Hanafy (IISWC, 2017)

CommAnalyzer: automated estimation of communication cost and scalability on HPC clusters from sequential code. - Ahmed E. Helal; Changhee Jung; Wu-chun Feng; Yasser Y. Hanafy (HPDC, 2018)

Exploring FPGA-specific Optimizations for Irregular OpenCL Applications. - Mohamed W. Hassan; Ahmed E. Helal; Peter M. Athanas; Wu-Chun Feng; Yasser Y. Hanafy (ReConFig, 2018)

Domain-Specific Modeling and Optimization for Graph Processing on FPGAs. - Mohamed W. Hassan; Peter M. Athanas; Yasser Y. Hanafy (ARC, 2021)