A single-chip SC line equalizer system for full duplex multi-bit rate digital transmission. - Kenji Nakayama; Yutaka Takahashi; Yayoi Satoh; Masahiro Naka; Yasuaki Nukada (ICASSP, 1986)

An adaptive line equalizer LSI for ISDN subscriber loops. - Daijiro Inami; Yoshiaki Kuraishi; Shigeo Fushimi; Yutaka Takahashi; Yasuaki Nukada; Shigeharu Kameyama; Akihiro Shiratori (IEEE J. Solid State Circuits, 1988)

A single-chip 16-bit 25-ns real-time video/image signal processor. - Katsumi Kikuchi; Yasuaki Nukada; Yasuhiro Aoki; Toshiyuki Kanou; Yukio Endo; Takao Nishitani (IEEE J. Solid State Circuits, 1989)

An analog front-end chip set employing an electro-optical mixed design on SPICE for 5-Gb/s/ch parallel optical interconnection. - Takeshi Nagahori; Kazunori Miyoshi; Yukio Aizawa; Yuki Kusachi; Yasuaki Nukada; Nobuharu Kami; Naofumi Suzuki (IEEE J. Solid State Circuits, 2001)