Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering. - Yasue Yamamoto; Takeshi Hidaka; Hiroki Nakamura; Hiroshi Sakuraba; Fujio Masuoka (IEICE Trans. Electron., 2006)

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. - Yasue Yamamoto; Masanori Shirahama; Toshiaki Kawasaki; Ryuji Nishihara; Shinichi Sumi; Yasuhiro Agata; Hirohito Kikukawa; Hiroyuki Yamauchi (IEICE Trans. Electron., 2007)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. - Yasue Yamamoto; Atsushi Kawasumi; Shinichi Moriwaki; Toshikazu Suzuki; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2012)

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. - Shinji Miyano; Shinichi Moriwaki; Yasue Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2013)